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Ph.D. Defense: Yongsuk Choi


442 Dana

April 15, 2015 10:00 am
Cost: Free
April 15, 2015 10:00 am

Scaling of integrated circuits (ICs) enables continuous improvement of the operation frequency on many processor and memory capacity. On the contrary, bus performance and I/O channel speed have not been followed the growth. The link speed is limited by the channel bandwidth due to its low pass filtering characteristics. To extend the channel bandwidth, increase signal integrity and achieve multi-Gb/s date rates, channel equalization is an essential technique in I/O part.

One of a common topology is decision-feedback equalizer (DFE), a nonlinear equalizer design applicable at multi-Gb/s date rates. In the DFE, the sampler and summer are the main blocks. In conventional design approaches, current-mode designs are chosen because of its speed while consuming high power. In this work, on the other hand, the summer block is included in the sampler in order to achieve an efficient trade-off between power consumption and operational speed. In addition, the sampler is designed as a cascode structure which increases kick-back noise immunity and reduces power consumption by 11%.

In this proposal, a wireline receiver design at 10 Gb/s data rate has been presented. A power efficient continuous-time linear equalizer (CTLE) and 1-tap look-ahead decision feedback equalizer are designed and implemented in 45nm CMOS technology to demonstrate the bandwidth compensation functionality. The channel model is used to construct a chip-to-chip link for board level communication. The channel loss at Nyquist frequency is 15dB. Also, the PLL used in the proposed receiver drives 5 GHz clock frequency with 12.62 ps peak-to-peak jitter. The core receiver circuit consumes 14.3mW at a 1.1 V supply voltage when processing 10Gb/s data rate.

Prof. Yong-Bin Kim (advisor)
Prof. Fabrizio Lombardi
Prof. Marvin Onabajo