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ECE Seminar: "A Network-on-Chip Architecture for flexible Neural Network Implementation," Dr. Vipin Kizheppatt, Nazarbayev University

18
Jul

442 Dana

July 18, 2018 10:00 am
July 18, 2018 10:00 am

Speaker: Dr. Vipin Kizheppatt, Nazarbayev University

Title: A Network-on-Chip Architecture for flexible Neural Network Implementation

Abstract:

Traditional neural networks depend on modifying the weights of neural synapses to train them. The connectivity between the neurons remain intact in all these architectures. Such architectures are quite suitable for classification and detection applications. Implementing high-level cognitive functions require much more than such traditional architectures. Neurons in our brain implement cognitive functions using different mechanisms. Here connections between neurons are very dynamic and the training does not solely depend upon the synaptic weights. Recently an artificial neural network architecture called hierarchical temporal memory (HTM) is proposed to emulate brain neural networks. In this work we investigate how network on chip (NoC) architectures can efficiently implement such dynamic neural network architectures. Implementing such NoC architectures on cloud-based reconfigurable instances (such as F1 instances) will provide scalable and high-performance neural network-based applications.    

Bio:

Dr. Vipin Kizheppatt is an assistant professor with the department of electrical and computer engineering at Nazarbayev University. He completed his PhD in reconfigurable computing in 2015 from Nanyang Technological University, Singapore. From 2007-2010 he was an FPGA design engineer at Processor Systems India, Bangalore and from 2015-2017 he was an assistant professor at Mahindra Ecole Centrale (Indian campus of Centrale Supelec, Paris), Hyderabad, India.