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ECE PhD Defense: "A Process and Temperature Tolerant Low Power Semi-Self Calibration of High Speed Transceiver for DRAM Interface," Ho Joon Lee

04
Dec

310 Dana

December 4, 2015 12:00 pm to 1:30 pm
December 4, 2015 12:00 pm to 1:30 pm
Abstract: 

As the demands for high volume data exchanges increase in many fields such as multimedia and telecommunications, significant efforts have been devoted to improve chip I/O performances to achieve high bandwidth. However, impedance mismatch between I/O driver and a transmitting channel causes signal reflections which interfere with the incoming data in terms of overshoot, undershoot or ringing. To ensure high quality signal integrity at the data rate beyond several gigabit per second, high-speed interfaces require minimum variations of output voltage level and slew rate over PVT variations.

This thesis presents a novel process and temperature variation compensation technique for semi-self impedance calibration of the transmission line driver. Based on the impedance mismatch analysis, a new semi-self impedance calibration circuit for high speed transceiver design is proposed to compensate the driver impedance mismatch caused by the process and temperature variation using process and temperature monitoring circuit. In this thesis, the Low Voltage Swing Terminated Logic(LVSTL) using a VSSQ termination and an adaptive calibration scheme are proposed. The LVSTL generates high frequency low voltage-swing signals with the VSSQ termination to reduce power consumption along with slew-rate control circuits. 2 stacked PU/PD network circuit are designed and each PU(Pull-UP)/PD(Pull-Down) network has two data inputs with the delay of the input data to control the slew rate of the inputs. VOH drift control scheme is also presented to address the VOH drift issue of VDDQ raised by NMOS rather than PMOS. To prevent the VOH drift phenomenon, a weak NMOS transistor is connected in parallel with NMOS PD transistor to provide a leakage path, resulting in a reduced but fixed VOH level. The impedance calibration in the pull-up and pull-down networks of the driver circuits are analyzed and designed based on the JEDEC LPDDR4(Low Power Double Data Rate) standard. In the receiver end, due to the low level of the common-mode voltage, the PMOS input amplifier is implemented and simulated. This thesis proposes a self-calibration loop and low noise amplifier that are adaptively controlled against process and temperature variations by employing a programmable active load and using process corner and temperature sensors so that the receiver amplifier amplifyies the arriving input data with a constant and enough gain for a safe data recovery. Test methodology to verify the proposed calibration scheme is presented using 11 stage ring oscillator. The proposed circuit is designed and implemented, also post-layout simulation has been done with all of the proposed impedance calibration circuits with 180nm CMOS technology using 1.8V supply voltage. With the proposed semi-self calibration circuit, VOH level change due to process variations is reduced by 81% in pull-up and 74% in pull-down networks without power overhead because it is foreground calibration scheme.

 

Advisor: Yong-Bin Kim

Committee Members:
Professor Fabrizio Lombardi 
Professor Marvin Onabajo