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ECE PhD Defense: Chun-hsiang Chang


442 Dana

November 19, 2015 10:00 am
November 19, 2015 10:00 am

Title: "Radio Frequency and Analog CMOS Integrated Circuit Design Methods for Low-Power Medical Devices with Wireless Connectivity"

Abstract: The ongoing improvements of complementary metal-oxide semiconductor (CMOS) technologies are enabling the integration of an increasing number of analog and digital circuits into single chips, which is a trend that continuous to result in performance enhancements and smaller portable electronic devices with wireless connectivity. A major challenge is that the radio frequency (RF) front-end section consumes excessive power in many new battery-powered wireless devices. For this reason, it is essential to create novel analog circuit design methods with significant power reductions for short-range communication applications. 

In this dissertation, linearity enhancement techniques for analog RF front-ends are proposed and demonstrated with a subthreshold low-noise amplifier (LNA) and an active down-conversion mixer. The linearization methods involve extra passive components to accomplish partial cancellation of third-order nonlinearity products, thereby reducing the distortion caused by subthreshold biasing to enable more widespread adoption of low-power design techniques. A 1.8GHz LNA was designed and fabricated using 0.11µm CMOS technology to proof the concepts. Measurement results reveal that the linearized low-power LNA has a 15.2 dB voltage gain, a 3.8dB noise figure, and a -3.7dBm third-order intermodulation intercept point (IIP3) with a power consumption of 0.336mW. Another 2.1GHz LNA fabricated in 0.13µm CMOS technology has a 9dB voltage gain, a 5.8dB noise figure, and a 0dBm IIP3 with a power consumption of 0.3mW. A low-power RF receiver frond-end (LNA and mixer) was also fabricated in 0.11µm CMOS technology and evaluated with measurements. The 1.95 GHz RF front-end has 20.6dB voltage gain, a 6dB double-side band noise figure and a -10.8dBm IIP3 with a power consumption of 0.9mW.

Another product of this research is an input impedance boosting method that was developed for long-term monitoring of electroencephalography (EEG) signals. An instrumentation amplifier (IA) having a power consumption of 93.6μW in 0.13μm CMOS technology was designed with a negative capacitance generation technique to cancel the adverse effects of input capacitances from the electrode cables and printed circuit boards. The IA with negative capacitance generation feedback (NCGFB) does not consume any extra power to boost the measured impedance from below 40MΩ to above 500MΩ at 50Hz after proper adjustment of its digitally programmable capacitors when the equivalent capacitance at the input is 150pF. Based on simulation and measurement results, the important instrumentation amplifier performance parameters are not significantly affected by addition of the proposed input capacitance cancellation technique.


Advisor: Professor Marvin Onabajo
Committee Members:
Professor Marvin Onabajo
Professor Yong-Bin Kim
Professor Nian Sun