You are here

ECE MS Thesis Defense: "Low-Power RF Circuit Design and Built-In Test Current Generation Techniques for Wireless Chips in Emerging Sensing Applications," Li Xu


442 Dana

March 2, 2016 12:00 pm
March 2, 2016 12:00 pm


Significant improvements of low-cost energy-efficient integrated circuit designs with sensing, analog signal processing, power management, computation, and communication functions are required to support the envisioned Internet of Things (IoT). Considering the goal to produce more portable wireless terminals and devices that communicate with each other, a critical obstacle is that radio frequency (RF) front-ends consume excessive power in many emerging wireless devices. It is essential and challenging to create novel analog circuit design techniques with significant power reductions while maintaining adequate performance. Another trend is that soaring wireless connections and the associated interference signals increase the demand for highly linear analog circuits in receivers to avoid that the desired signals are distorted by unwanted mixing with interference signals. This problem motivates research efforts to improve the third-order intermodulation performance of RF front-end circuits to minimize signal distortions. The design approaches developed in this thesis work simultaneously address the challenges of achieving low power consumption and high linearity, especially for RF front-end circuits operating with supply voltages below 1V and having power consumptions below 1mW. In particular, this research focuses on a linearization technique for low-power active mixers, which are often the bottleneck of the overall linearity performance in RF receiver front-ends. The concepts are demonstrated with a 2.4GHz RF front-end composed of a low-noise amplifier and mixer. This RF front-end was designed and fabricated in 130nm complementary metal-oxide semiconductor (CMOS) technology. It consumes 0.77mW with a 0.7V supply voltage, while having a measured in-band third-order intermodulation intercept point (IIP3) of -4.5dBm, a noise figure (NF) of 6.3dB, and a spurious-free dynamic range (SFDR) up to 62.8dB.

Another aim of this research has been to create circuits for the realization of next-generation portable wireless medical monitoring systems. Towards this goal, an on-chip test current generator was designed and integrated into an analog front-end with input impedance self-calibration for electroencephalogram (EEG) signal measurements. The test current generator includes a temperature-compensated relaxation oscillator, a limiter, and a custom operational transconductance amplifier (OTA) with sub-nanosiemens transconductance and high output impedance. The test current generator enables the injection of a 1pA alternating current into the inputs of an instrumentation amplifier for input impedance estimation based on current injection combined with amplitude detection. The test current generator was designed and fabricated in 130nm CMOS technology, and its functionality was validated with measurements of a test chip that includes the circuits in the signal path of the analog front-end for EEG monitoring applications.

Advisor: Professor Marvin Onabajo

Professor Marvin Onabajo
Professor Yong-Bin Kim
Professor Nick McGruer