General Purpose Graphics Processing Unit (GPGPU)s are frequently used to accelerate the performance of many types of parallel scientific and engineering workloads. The advent of GPU programming frameworks, such as Nvidia CUDA and OpenCL, has made it far easier to program these devices by providing a familiar C-syntax programming environment. Along with the increased popularity of these accelerators, comes an increased demand for simulation software that is capable of emulating their performance. Such computer architecture simulation software can be immensely useful in the performance benchmarking of hardware and Instruction Set Architecture (ISA) design decisions, and can be used to influence future microarchitectures.
One such heterogeneous simulator capable of emulating the Nvidia Kepler device is Multi2Sim. This research uses small programs called microbenchmarks that are designed to reveal microarchitectural properties in order to develop an understanding of the memory access timings and cache parameters inherent in the Kepler memory hierarchy. This knowledge is then integrated into the Multi2sim Kepler model to improve simulation accuracy.
These enhancements are shown to improve the timing accuracy of the Multi2Sim Kepler model by 11.3-38.3% for memory intensive benchmarks as compared to physical hardware.
- Professor David Kaeli (Advisor)
- Professor Gunar Schirner
- Professor Rafael Ubal Tena