Digitally-assisted integrated circuit design has gained popularity in recent years due to challenges associated with analog components in mixed-signal systems-on-a-chip, which include process variations, mismatches, and increased demand for circuit complexity in sub-micron fabrication process technologies. To optimize efficiency and cost, the focus during hardware design is increasingly directed on the creation of reliable and robust circuits that are immune to variations and unpredictable factors out of the designer’s control. On the other hand, the circuits should be power and area efficient to adapt to the needs associated with portable devices, wireless communications, and the global energy and cost saving trends. On-chip calibration techniques can be developed to address these issues by reducing the sensitivity of analog circuit designs, thereby improving their universal usefulness and scalability. Another emerging trend is the rising demand for high-speed low-power analog-to-digital converters (ADCs) to accommodate the increased use of digital processing and big data. The research described in this thesis unites these topics in a design approach for ADCs.
This thesis introduces the design of a 3-bit flash ADC with an offset calibration scheme, which is integrated into a two-step 8-bit hybrid flash/successive approximation register (SAR) architecture with time-interleaving. Due to the hybrid architectural structure, the offset requirement for the flash ADC is more stringent than for a conventional standalone 3-bit ADC. Two pairs of transistors are employed to adjust the offsets for each of the seven comparators in the flash ADC by creating a current flow imbalance between the comparator’s branches. The amount of current injected in each branch is controlled through the gate voltages of the calibration transistors, which are generated with automatic on-chip calibration circuitry that was developed as part of this research. The circuits were designed, simulated, and fabricated using 130nm complementary metal-oxide semiconductor (CMOS) technology. The calibration path emulates the ADC’s normal operation to establish realistic loading and transient effects. Furthermore, the design approach addresses integration challenges within the hybrid ADC system, such as kickback noise and common-mode variations. Monte Carlo simulation results show that the offset standard variation is reduced from 19.2mV to 0.582mV (worst case) through the calibration. The power consumption of all digital circuits (not including calibration circuitry) is 1.36mW from a separate 1.2V supply, and the power consumption of the calibration logic with a 10MHz clock is 0.60mW. The dynamic latched comparator of the flash ADC with kickback reduction was evaluated with post-layout simulations including process-voltage-temperature (PVT) variations. It has a 231ps propagation delay, and consumes 0.16mW. From simulations of the flash ADC, the worst-case effective number of bits (ENOB) is 2.88, and the worst-case signal-to-noise-and-distortion ratio (SNDR) is 19.1dB in the slow process corner case with a temperature of 85 degree Celsius, 1.14V supply, and low input frequency (2.923MHz). The flash ADC consumes 3.6mW. The comparator design incorporates a kickback reduction technique that reduces the kickback effect from 23.3mV to 1.2mV for a 500mV input during system-level simulations. Measurements of a prototype chip show that the ENOB improves from 3.64 to 5.24 bits using a 500MHz clock during automatic calibration.
- Professor Marvin Onabajo (Advisor)
- Professor Yong-Bin Kim
- Professor Aatmesh Shrivastava
- Dr. Hari Chauhan