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ECE MS Defense: "CMOS Low Power Digital and Analog Subthreshold Temperature Sensor Design," Yun Seok Hong


309 Dana

July 2, 2018 1:00 pm
July 2, 2018 1:00 pm

Sensing temperature for localizing hot spots provides additional observability in modern integrated circuits. First, a digital temperature sensor with modified inverter interlaced cascaded delay cells (IICDCs) is presented.  Temperature is sensed by using a temperature-to-pulse generator that produces pulse with an XOR gate and a temperature dependent delay line with the modified IICDCs. A D flip-flop based T flip-flop is implemented to produce a pulse, which is used as the input signal of the delay line, and the inverted input signal is employed to reduce the offset of temperature sensor. The output of the temperature-to-pulse generator is applied to a time-to-digital converter (TDC) to achieve digital codes of the sensed temperature. By using the modified IICDCs, it is possible to consume lower power than the conventional approach using the inverter-based delay lines.  

The digital temperature sensor is designed with 180 nm CMOS technology and 1.8 V supply voltage. This digital temperature sensor circuit consumes 324 uW at 27 degree Celsius. The temperature sensor monitors -20 to  110 degree Celsius with a good linearity. Second, an analog subthreshold voltage temperature sensor is presented. In the previous subthreshold voltage temperature sensor topology, a PMOS transistor array is employed to monitor temperature variation. Once the temperature sensor is completely pre-charged, the PMOS transistor array begins discharging.

When the PMOS array enters weak inversion, the sampling point is decided. The existing low power subthreshold voltage temperature sensor requires complicated weak inversion current equation to choose the optimal sampling time. To reach the optimal sampling time, it takes approximately 10 to 100 uS. In the proposed analog subthreshold temperature sensor, PMOS transistor is employed to monitor temperature variation. When the PMOS enters weak inversion in discharging process, the PMOS stops discharging and the output node voltage becomes stable. It takes around 4 uS. To remove the exponential term in the weak inversion current equation, a summing amplifier is used, and the output node is connected to an analog-to-digital converter (ADC) to change the temperature information to the digital code.  

The supply voltage of the analog temperature sensor is 1.8 V, and the 180 nm CMOS technology is used to design the analog temperature sensor. The total power consumption of the analog temperature sensor circuit is 2.5 mW at 27 degree Celsius. The front-end of the temperature sensor consumes
11.19 uW. The analog temperature sensor can monitor from -20 to 130 degree Celsius and shows a very good linearity.

  • Professor Yong-Bin Kim (Advisor)
  • Professor Fabrizio Lombardi
  • Professor Marvin Onabajo