Silicon-on-insulator ResearchSilicon-on-insulator Research
Recent advances in silicon-on-insulator(SOI) technology has generated increased interest in their application to high speed CMOS circuits. The speed advantage is a direct consequence of the insulating layer which provides isolation from the substrate thereby decreasing capacitances for both devices and electrical interconnections. In addition, total electrical isolation of individual transistors results in complete latch-up immunity leading to smaller device size and higher packing densities.
A new area of interest is the potential application of SOI materials to micromechanical structures. Such structures can be applied to physical, chemical and optical sensors. The advantages of SOI for these applications are derived from the existence of an insulating layer between the active silicon and the substrate. During the fabrication of mechanical structures, the underlying silicon oxide can become a sacrificial layer that is etched away at the end of the process to free the mechanical structure. Structures such as beams, cantilevers and even diaphragms can be formed in this fashion.
SOI has also demonstrated high temperature capability with CMOS circuits. Its high temperature performance allows the fabrication of signal conditioning circuits on the same chip and near the sensing element. Sensors are often located in harsh environments where high-temperature operation can be important. The marriage of SOI's mechanical properties with its high temperature circuit operation would provide performance unobtainable with other technologies.
Sensors built on bulk silicon are designed with conventional electronics in mind and are therefore subject to the bulk silicon temperature restrictions(typically <125 C). This practical limitation reduces the broad application of intelligent sensors using bulk silicon electronics.
In SOI, a single crystal silicon layer is separated from the silicon wafer by a thin oxide. Devices fabricated in SOI using conventional CMOS fabrication techniques have demonstrated substantially better high temperature characteristics than equivalent bulk devices [1]. Large (l = 50 um) enhancement mode p- and n-channel MOSFETs fabricated in Zone-Melt-Recrystallized (ZMR) SOI have demonstrated much lower leakage current for ZMR SOI devices as as compared with bulk silicon (Figure 1).
One of the surface micromachined devices we are developing is a capacitive pressure sensor. The device is constructed using ZMR SOI with a 1 micron epitaxial silicon layer and a 1 micron silicon dioxide insulator. The epitaxial silicon layer is used to form the diaphragm of the sensing capacitor and to form the upper plate of the reference capacitor. The silicon dioxide layer is used as a sacrificial support structure under the diaphragm and as a dielectric for the reference capacitor. The clamp structure used to support the diaphragm can be constructed of polysilicon or silicon nitride. The use of silicon nitride reduces the parasitic capacitances associated with the clamp structure.
This device uses a port etched in the substrate which allows differential pressure measurements and serves as access to the sacrificial oxide layer under the diaphragm. Twenty six sensors of varying sizes are included on a die, one half of which are square and the remainder circular. The square sensors range in size from 50 microns to 2000 microns on a side providing a maximum pressure of 265 psi to 1x10-4 psi. The circular sensors range in size from 27 microns to 1000 microns in radius providing a maximum pressure of 250 psi to 1.3x10-4 psi. Included with each sensor is a reference capacitor surrounding the device.
The process shown in Figure 2 begins with a 23 mil, 3" (100) oriented ZMR SOI wafer with a 1 micron epitaxial silicon film and a 1 micron buried oxide. The wafer is backlapped and polished to 22 mils in preparation for backside processing. The epitaxial silicon is patterned in a RIE. The oxide layer is isotropically etched to remove the exposed oxide down to the substrate and to slightly undercut the silicon structures. This undercut will form the lower portion of the clamp structure which will support the diaphragm when etched free. A thin silicon nitride layer is deposited to act as a mask for the backside port etch. This layer must protect the substrate and patterned epitaxial silicon layer during the long KOH etch that follows. The backside is patterned in an infrared aligner and then the nitride is etched by RIE. The ports are then etched in KOH to a point. A TMAH etch with a lower degree of anisotropy is used to break through to the oxide under the devices and complete the port openings. The thin nitride is removed in phosphoric acid and a thick (1 micron) silicon nitride layer is deposited to act as the diaphragm clamp structure. The silicon nitride is oxidized and the front is patterned. This patterning step exposes the silicon diaphragms and reference capacitors. The wafer is etched by RIE to clear the oxide and to begin etching the nitride. After stripping the PR mask, the nitride etch is completed in phosphoric acid. Chromium is deposited and patterned to contact the diaphragm, the reference capacitor and the substrate. Additionally, a guard ring between the reference and the diaphragm is formed in this metal layer. The wafer surface is coated to protect the nitride clamp during the long HF etch. When the etching is complete, the wafer is rinsed in water, cleaned in sulfuric/peroxide, rinsed in water and immersed in alcohol. Drying is accomplished at 130 C by evaporating the alcohol.
In order to exploit the high temperature advantages of SOI as a sensor material, its mechanical and electrical properties have to be determined. The following paragraphs provide a brief description of the work performed to date in this area.
A diagnostic mask was prepared for the evaluation of the strain in ZMR films. The majority of the strain diagnostic structures have been reported by Guckel, et al [3,4,5]. These include doubly supported beams used for the analysis of compressive stresses and ring and beam structures used for tensile stress measurement. In addition, we have included the spiral structures reported by Long-Sheng Fan, et al [6] for the evaluation of stress non-uniformity with film thickness.
A new test structure was designed at Northeastern for measuring orientation dependent tensile stress. It consists of two support posts used to anchor long thin angled beams which connect to two vernier position measuring features as shown in Figure 3. Three of these structures are needed to cover six orders of magnitude of tensile stress. The operation of the structure is simple. Under tensile stress conditions, the angled beams when etched free of the substrate release their stress by bending. This bending reduces the angle and increases the separation between the two center position measurement features The distance these features move can be determined by observing the alignment of the two comb structures. In each comb, subsequent prongs are two microns longer than their neighbor to the right. Under unstressed conditions, the right most prongs overlap by two microns. Increasing the stress will cause the first prong of the lower comb to come into vertical alignment with the second prong on the upper comb. This would indicate a motion of 1 micron for each comb. As stress increases further, subsequent prongs come into alignment. Using the vernier arrangement shown, it is a relatively simple matter to measure the relative motion of the combs to within one micron.
In the ZMR SOI, we found an anisotropy in the strain in the epitaxial layer exhibiting no measurable strain in the [100] direction of the scan and a strain of 3.08e-4 in the [010] direction.
SOI wafers with one micron silicon epitaxial films on one micron of silicon dioxide were obtained on (100) oriented 10 ohm-cm phosphorous doped substrates. The wafers were patterned with a piezoresistor mask set that created a number of test and reference resistors. The resistors were doped at four levels; 5x1017/cm3, 2x1018/cm3, 7x1018 cm3, and 1.8x1019/cm3 respectively. Each wafer was processed to create five samples, each about 0.5" wide and about 1.5" long as shown in Figure 4 below.
The sample was clamped near its mid point so that one end of the beam could be deflected. The clamping point was defined by two markers to the left of the piezoresistors. The six piezoresistors to be measured were patterned near the clamp on the side undergoing deflection in pairs of three orientations: longitudinal, diagonal and transverse. The resistors share a common electrical return. Two additional resistors at the unstressed end of the beam near the contact pads were defined and used as controls during the measurement. In addition, a four point resistivity structure and a metal contact resistance structure were included as a check on our process.
After the wafers were processed and diced, a single sample was loaded into a sample holder for testing. Measurements were made inside an oven whose temperature was adjusted in the range between about 25 C and 150 C. Two terminal resistance measurements were made on all eight resistors at twenty strain levels. In addition, the resistance of the unstrained sample before and after the measurement was recorded.
Measurements of the gauge factor (Figure 5) and the temperature coefficients of the gauge factor (Figure 6) and the resistance (Figure 7) show that the ZMR material has properties similar to single crystalline silicon as reported by Tufte and Stelzer[8]. The main differences between ZMR and single crystalline silicon are in the temperature coefficients of the resistance and gauge factor. Based on these results, it should be possible to fabricate high quality pressure sensors using SOI wafers based on the ZMR process.
