Wafers for CHEX

In the fall of 1994 and spring of 1995, the Northeastern University Microfabrication Laboratory undertook the task of processing wafers for the CHEX program.  In order to satisfy the needs of the program, the wafers were required to meet strict specifications.  These included specifications on the surface quality of the wafers and on their dimensional tolerances.  The most difficult specification was that imposed on the surface finish.

One and one half inch silicon wafers were supplied by a commercial vendor (Virginia Semiconductor) with a thickness of 100 microns, or about twice the thickness of an average human hair.  A process was developed at Northeastern that involved a fundamental change in the design of the experimental apparatus planned for the CHEX program.  As originally conceived, the wafers were to be supplied with three holes.  These holes were to be used for alignment purposes in creating the stack.  Due to the difficulty of processing wafers with holes in them, Northeastern proposed that flats be fabricated around the periphery of the wafer instead.  Using this design and the etching techniques used by Northeastern, it was possible to create the flats and posts simultaneously.  This idea was considered and adopted by the CHEX Stanford team.

In order to meet the needs of the program, the wafers were to be thinned to 50 microns while leaving three large posts and many smaller posts distributed on the wafers surface.  In this way, when the wafers are stacked, the posts define the separation between wafers.  This region between wafers is what confines the liquid helium.  The posts were coated with an indium layer which acts as both a pad and a bonding layer.

A team was assembled at Northeastern with members listed below:
 

Team Member	Affiliation
Paul M.Zavracky	Northeastern University
Keith Warner	Northeastern University
Bob McClelland	Northeastern University
Greg Jenkins	Northeastern University
Celeste Fradet McClelland	Northeastern University
Bao Vu	Northeastern University
David Stricker	Stanford University
Bob Frazer	JPL

The initial program aimed at developing the tools and techniques required to produce wafers that met specification.  This included the development of handling methods for carrying 50 micron thick wafers, a nitrogen driven carousel etching apparatus, double sided alignment fixtures, and a double side exposure tool.  One of the unique aspects of the process was that the three flats were etch from both sides while the posts were etch from only one side.  Therefore, the completed formation of the flats was used to indicate the precise moment when the wafers were etch half way through.  This provided a high degree of control over post height.  A careful analysis of the etching process resulted in high quality surface finishes and was reported in the Journal of the Electrochemical Society¹.

A pilot production line was established with the Northeastern Microfabrication laboratory which included the dedication of all equipment required to produce the wafers, a staging area and an inspection area.  By the end of the six month program, over 1500 wafers had been produced.  Approximately 800 wafers were assembled into two stacks of 400 each, a primary stack used on the space shuttle and a back-up stack.
 

1 Q-B Vu, D. A. Stricker, and P.M. Zavracky, "Surface Characteristics of (100) Silicon Anisotropically Etched in Aqueous KOH," J. Electrochem. Soc., Vol. 143, No. 4, pp 1372, 1375, April 1996.

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