3D Computational Image Sensors For Advanced Low Power Visual Processing

Project Description

The 3D computational image sensors program proposes to develop sensors which will allow high speed, high resolution image processing in compact low power portable systems. These systems will be combined with high density optical storage media operated through a belt-worn read/write driver to provide rapid storage and retrieval of information.

The major obstacle at present to building compact, low power systems for complex visual processing is the planarCOPS process. The restriction to two dimensions severely limits the type and number of concurrent communicating processors which can be placed on a single chip or linked across chip boundaries. The research team at Northeastern University will develop, in conjunction with Kopin and Polaroid Corporations, the technology required to build 3-dimensional structures combining large array imagers with stacked interconnected processing layers. The proposed technology is radically different from current approaches for 3D integration which involve advanced packaging techniques, such as multi-chip modules (MCMs), and which require interconnect lines to be brought to the periphery of the chip stack. Our technology will allow virtually unrestricted placement of vias connecting the stacked processing layers within the interior of the chip. We can thus envision connecting each pixel of the image acquisition layer to an underlying processing element to perform massively parallel processing operations.

Approach

The approach to be pursued is based around the Kopin Corporation transfer circuit technology combined with sub-pixel-sized vertical interconnects. The technology to be developed includes improving the transfer and alignment processes and reducing via size to less than 3 microns. In a previous program funded by ONR to design a 3D microprocessor, Northeastern University developed the technology to fabricate 16 micron vias. For an image sensor, a small via size of < 3um is critical to realizing a high density imaging array on a die size of 1 cm square.

Each layer will be processed through a foundry in a CMOS process optimized for SOI material. The top-most layer of the 3D sensor will include the imaging function and will require fabrication of an array of active pixels, each containing an active device to drive its signal vertically through an interconnect onto the first processing layer. The processing layers will include circuits for performing image filtering in the analog domain, low power A/D converters, memory buffers, and isolated digital processing elements for specific computations, all optimized for design in SOI technology

Project Tasks

• Prototype System Development and Integration
• Phase I: CMOS imager with flash memory
• Phase II: Preliminary 3D imager with optical disk storage
• Phase III: Advanced 3D smart sensor with portable read/write optical disk
• 3D Process Development
• Small via technology development (< 10 microns)
• Decrease via size (< 3 microns)
• Transfer and alignment process improvement for multi-layer stacks
• Image Acquisition in 3D structure
• Design image acquisition layer for 3D integration
• Fabricate and characterize 2-layer imaging device
• Combine imaging layer with advanced processing layers
• 3D Computational Sensor Design for Applications
• Adapt CAD tools
• Build test analog circuits in SOI
• Design application specific processing layers

Project Status

This 36 month program was awarded in June 1996.

• An initial test chip to characterize devices on the imaging layer has been fabricated and is currently undergoing testing.
• We are preparing a second test run to be fabricated in January 97 to characterize both the imaging layer and a readout layer in SOI.
• The design of the Phase I prototype system has been completed and construction has begun. The first system will be delivered in early 1997.

October 1996