1. (8) 7.11

2. (3) 7.12

3. (12)

a. Plot the drain current as a function of VDS for VGS = 0.5, 0.75, and 1.0 V for both PMOS and NMOS transistors based on the 2009 goals in the ITRS 2007 Roadmap: effective tox=1.04 nm, W=1 micron, L=16nm, Vt = +/- 100mV, and maximum VDS=1V. Assume a saturation velocity of 5e6 cm/s and low-field mobilities of 500 and 200 (cm2/V-s)for electrons and holes in the channel.

b. For comparison, on a second plot, plot the characteristics from the simple model on the same axes as the characteristics with velocity saturation from a..

4. (8) 8.1

5. (16) Referring to the two papers on intel high-k/metal gate technology (see course web site), answer the following questions.

a. Why are high-k dielectrics required?

b. What oxides are most often investigated for this application?

c. What are drawbacks to high-k technology in transistor performance?

d. What are "midgap metals"?

e. What are n+ and p+ metal gate electrodes?

f. How was it determined that phonons are the major contributor to reduced mobility in the high-k/metal gate transistors tested?

g. What measurements showed that the number of interface traps in the high-k transistors is not excessive? Explain why this measurement would show interface traps, considering the changing charge in the interface traps.

h. What measurements showed that the amount of fixed charge in the high-k transistors is not excessive? Explain the principal of the measurement based on your knowledge of threshold voltage.