ECE 1406, Homework #6, Due May 27, 2003
1. Referring to the article "The Amazing Vanishing Transistor Act, IEEE Spectrum:"
a. What parameter in the drain current equation is improved by using a strained silicon layer?
b. How is the strain introduced into the lattice?
c. When is this technology likely to be adopted?
d. Why are high k gate oxides needed?
e. What will be improved if high k materials prove to be successful?
f. What parameter seems likely to be degraded when using high k materials?
g. What advantages do metal gates have over poly?
h. What is the main advantage of using a double gate?
i. In what products is the double gate likely to appear in first?
j. If the channel is doped at a level of 3x1017 cm-3, how many dopant atoms are present in the whole channel if the dimensions are 0.03x0.15x0.03 microns?
2. Referring to the article "Fast Films, IEEE Spectrum:"
a. What are disadvantages of low k materials as compared with silicon dioxide?
b. How would use of low k materials save a company money?
c. What are the two competing methods used to apply low k films?
d. Which method is capable of producing lower k films?
e. Which is more expensive?
3. Referring to the article "One Billion Transistor Processor, Who Will Be the First?:"
a. How has the necessary planarity been achieved for leading edge lithography?
b. Why is the gate length made smaller than the nominal process dimension (smaller than the 1/2 pitch)?
c. What interlevel dielectric is used between metal layers in the pentium chip?
d. What high k material looks most promising for the near future?
e. What is an alternative material?
f. What materials changes are being considered for the gate?
g. What change in the substrate is anticipated?
h. What interconnect system is likely to be used?
i. What could be used in the future to avoid RC delays?