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1998 VLSI Circuits Symposium Memory Design Workshop Agenda - June 10th

South Pacific Ballroom

Chair Persons:      Wah Kit Loh, Texas Instruments and Chang Hyun Kim, Samsung Electronics

Period

Topic

Proposed Presenter

Time

1

Evolution of DRAMs

Peter Gillingham (MOSAID)

8:05am-9:00am

2

Comparative core design techniques

Derek Nuhn (Semiconductor Insights)

9:00am-10:00am

3

BREAK --- 10:00am-10:15am

4

High speed clock synchronization and distribution with emphasis on DLL principles and design

John Maneatis (SGI)

10:15am-11:15am

5

Approaches to low power designs

Chang Hyun Kim (Samsung)

11:15pm-12:15pm

6

LUNCH

---

12:15pm-1:15pm

7

Redundancy for maximum yields

Brent Keeth (Micron)

1:15pm-2:15pm

8

Voltage regulation at low voltages

Yoshinobu Nakagome (Hitachi)

2:15pm-3:15pm

9

BREAK

---

3:15pm-3:30pm

10

Design-In-Reliability

Tony Leigh (Texas Instruments)

3:30pm-4:30pm

11

System level performance analysis with multi-memory masters.

Jeffery Lee (NEC)

4:30pm-5:30pm