Memory Design and Evolution Short Course

This one day Memory Design Short Course focuses on design techniques used on and challenges encountered by the latest generations of Dynamic RAM ICs. 
 

Who should attend

This short course is tailored for both systems and circuit designers who plan on understanding and using the latest generations of DRAMs. Experience with digital systems and basic knowledge CMOS circuit design is assumed. Basic knowledge of the DRAM architectures is helpful, although not required.  

What you will learn 

• Evolution of the DRAM
• SDRAM, DDR, SLDRAM, RAMBUS functions
• Designing digital delay locked loops 
• What is meant by Design In Reliability
• Voltage Regulator and Redundancy schemes
• Designing for low power
• System design issues with multi-memory masters

Chairpersons: Wah Kit Loh, Texas Instruments and Chang-Hyun Kim, Samsung Electronics

Memory Design Short Course Outline

• lntroduction to DRAMs and their evolution (Peter Gillingham, MOSAID)
• Latest product offerings
• State diagrams and specifications
• DRAM technology trends and their implications on circuit performance
• Core circuits development trend and comparative design techniques (Derek Nuhn, Semiconductor Insights)
• Sense amps, main amps, I/O buffers, data path schemes
• Array architecture trends for small chip size and high speed access
• Design implications of COB and CUB storage cells
• Sub-decoder schemes, hierarchical bitlines, I/Os, bits/WL, bits/BL trends
• High Speed Clock Syncronization and Distribution with emphasis on DLL Principles and Design (John Maneatis, SGI))
• Latching techniques
• Digital Delay Locked Loops and Synchronous Mirror Delay designs
• Lead frame design for inductance and capacitance minimization
• High speed I/O interfaces
• Approaches to low average and peak operating and standby currents (Chang Hyun Kim, Samsung)
• On chip capacitance filter structures
• Charge re-cycling schemes success and failures
• Redundancy approaches for maximum yield (Brent Keeth, Micron)
• Partitioning and replacement schemes
• Fuse construction
• Voltage regulation and pumping schemes in a low voltage world (Yoshinobu Nakagome, Hitachi)

• Design in Reliability in DRAMs (Tony Leigh, Texas Instruments)
• ESD, antenna effects, CHC, GOI, TDDB, EM, latch-up, ASER
• System level design considerations with multi-memory masters (Jeffery Lee, NEC)

Follow links for each of the above topics for a more detailed description.

This short course does not cover

• FLASH memory designs
• Embedded DRAMs and Application Specific DRAMs (ISSCC Feb. 1998 Workshop)
• Multi-level DRAMs as a stand alone topic
• Structural aspects of DRAM packaging
• Physical design verification
• High speed testing of DRAMs
• DRAM process technology challenges  (STI, CMP, DUV, CD control)
• System application trends (I/O options, internal bank number forecasts)
• TAM forecasts.

Location: South Pacific Ballroom

See Agenda

Go back to VLSI 1998 Symposia Homepage

Suggested reading prior to attending course:
Articles
- Trends in Semiconductor Memory
  IEEE Micro November/December 1997
- Advanced DRAM Architectures Overcome Data Bandwidth Linits
  Electronic Design, November 17, 1997 pg73-88
-Advanced DRAM puts you in the fast lane
  EDN October 9 1997, pg52-80
- Limitations and Challengers of Multi-gigabit DRAM Chip Design
  JSSC, May 1997

Books
High Performance Memories
Betty Prince
Wiley
ISBN 0-471-95646-5

Semiconductor Memories
Betty Prince
Wiley
ISBN 0-471-92465-2