Welcome to the 1998 Symposium on VLSI Technology. On behalf of the organizing Committees, we invite you to attend the 1998 Symposium on VLSI Technology to be held from June 9 - 11 in Honolulu, Hawaii.
The 1998 Symposium promises to be exciting. Over 230 excellent papers were submitted from all over the world. The Symposium continues to grow in size and importance. From this impressive roster, we selected 84 contributed papers organized into 22 sessions. We are also delighted to have two distinguished Invited Speakers for the Plenary Session. Dr. Kathleen Perry, Vice President of Obsidian Corporation, will speak on the evolution of CMP technology from lab curiosity to a mainstream production process. Dr. Masaru Sasago, Research Director, from the Association of Super-Advanced Electronics Technologies (ASET) will speak on the challenges ahead in advanced lithography.
Four Rump Sessions are planned for the evening of June 10th as a means to facilitate informal discussions among researchers. A Joint Session with the Symposium on VLSI Circuits will address "High Performance Technology for 1GHz Operation and Beyond". The three other sessions will cover specific technology related topics of timely interest:
A one-day Short Course, planned for Monday June 8, will cover "Advanced Processing and Devices Structures for Future ULSI". This should be an excellent opportunity for experienced as well as new engineers to broaden their technical base.
The Symposium registration fee covers all of the sessions including the Rump Sessions. Daily continental breakfasts and the banquet are also included. Registration for the Short Course is extra. The detailed registration fees and hotel reservation schedules are included in the Advance Program.
As in past years, we expect a strong participation from leaders of the VLSI industry and academic researchers. We look forward to an exciting Symposium in Honolulu. Please join us.
Tony Alvarez
Program Chairman
Masakazu Kakumu
Program Co-Chairman
| SESSION 1: Plenary Session [TAPA I/II/III] | ||
|---|---|---|
| Chairpersons: | A.R. Alvarez, Cypress Semiconductor M. Kakumu, Toshiba Corp. | |
| 8:30 | Welcome and Opening Remarks Bill Siu, Intel Corp. Masao Fukuma, Hiroshima University | |
| 8:45 | 1.1 | Chemical Mechanical Polishing: The Impact of a New Technology on an Industry Kathleen Perry, Obsidian Corp. |
| 9:25 | 1.2 | Lithography Solution for Sub 0.1u Generations Masaru Sasago, ASET |
SESSION 2: Highlights [TAPA I/II/III] | ||
| Chairpersons: | R. DeKeersmaecker, IMEC M. Kinugawa, Toshiba Corp. | |
| 10:20 | 2.1 | A High Performance 3.97um2 CMOS SRAM Technology Using Self-Aligned Local Interconnect and Copper Interconnect Metallization M. Woo, M. Bhat, M. Craig, P. Kenkare, X. Wang, F. Tolic, H. Chuang, S. Parihar, J. Schmidt, L. Terpolilli, et al., Motorola, Austin, TX |
| 10:45 | 2.2 | 1.5V Operation Sector-erasable Flash Memory with Bipolar Transistor Selected(BITS) P-channel Cells T. Ohnakado, N. Ajika, H. Hayashi, H. Takada, K. Kobayashi, K. Sugahara, S. Satoh and H. Miyoshi Mitsubishi Electric Corp., Hyogo, Japan |
| 11:10 | 2.3 | A 0.15u DRAM Technology Node for 4Gb DRAM K.N. Kim, H.S. Jeong, G.T. Jeong, C.H. Cho, W.S. Yang, J.H. Sim, K.H. Lee, G.H. Koh, D.W. Ha, J.S. Bae, J.G. Lee, B.J. Park and J.G. Lee Samsung Electronics Co., Kyungki-do, Korea |
| 11:35 | 2.4 | A High-Performance Sub-0.25u CMOS Technology with Multiple Thresholds and Copper Interconnects L. Su, R. Schulz, J. Adkisson*, K. Byer, G. Biery, W. Cote, E. Crabb‚, D. Edelstein, J. Ellis-Monaghan*, E. Eld, D. Foster, R. Gehres, et al., IBM Semiconductor R&D Center, Hopewell Junction, NY and *Essex Junction, VT |
| 12:00 | Lunch | |
SESSION 3: Cu Interconnects [TAPA I] | ||
| Chairpersons: | T. Seidel, Genus Corp S. Kawamura, Fujitsu, Ltd. | |
| 1:30 | 3.1 | An Inlaid CVD Cu Based Integration for Sub 0.25u Technology D. Denning, G. Braeckelmann, J. Zhang, B. Fiordalice and R. Venkatraman Motorola, Inc., Austin, TX |
| 1:55 | 3.2 | An Evaluation of Cu Wiring in a Production 64Mb DRAM W. Cote, G. Costrini, D. Edelstein, C. Osborn, D. Poindexter, V. Sardesai, and G. Bronner IBM Semiconductor R&D Center, Hopewell Junction, NY |
| 2:20 | 3.3 | Copper Drift in Low-k Polymer Dielectrics for ULSI Metallization A.L.S. Loke, J. Wetzel*, C. Ryu and S. Wong Stanford University, Stanford, CA and *Motorola, Inc., Austin, TX |
| 2:45 | 3.4 | A Cu/Low-k Dual Damascene Interconnect for High Performance and Low Cost Integrated Circuits B. Zhao, D. Feiler, V. Ramanathan, Q.Z. Liu, M. Brongo, J. Wu, H. Zhang, et al., P. Ding*, G. Lai*, B. Chin*, M. Johnson**, J. Turner**, T. Ritzdorf**, G. Wu# and L. Cook# Rockwell Semiconductor Systems, Newport Beach, CA and *Applied Materials, CA and **Semitool, MT and #Rodel, DE |
| 3:10 | Break | |
SESSION 4: Gbit DRAM Cells [TAPA II] | ||
| Chairpersons: | C. Dennison, Micron Technology C.-G. Hwang, Samsung Electronics Co., Ltd. | |
| 1:30 | 4.1 | The Impact of Isolation Pitch Scaling on VTH Fluctuation in DRAM Cell Transistors due to Neighboring Drain/Source Electric Field Penetration J.-H. Sim, J.-K. Lee and K. Kim Samsung Electronics, Korea |
| 1:55 | 4.2 | Improved 0.12u EB Direct Writing for Gbit DRAM Fabrication K. Nakajima, H. Yamashita, Y. Kojima, T. Tamura, Y. Yamada, K. Tokunaga, T. Ema, K. Kondoh, N. Onoda and H. Nozue NEC Corp., Kanagawa, Japan |
| 2:20 | 4.3 | A 0.21um2 7F2 Trench Cell with a Locally-Open Globally-Folded Dual Bitline for 1Gb/4Gb DRAM C. Radens, U. Gruening*, M. Weybright, J. DeBrosse, R. Kleinhenz, H. Hoenigschmid*, A. Thomas, J. Mandelman, J. Alsmeier* and G. Bronner IBM, Hopewell Junction, NY and *Siemens Components, Inc., Hopewell Junction, NY |
| 2:45 | 4.4 | A Novel Pillar DRAM Cell for 4Gbit and Beyond H.J. Cho, F. Nemati, P. Griffin and J. Plummer Stanford University, Stanford, CA |
| 3:10 | Break | |
SESSION 5: Advanced Interconnect [TAPA I] | ||
| Chairpersons: | C.S. Pai, Lucent Technologies, Bell Labs H. Hanafusu, Sanyo Electric | |
| 3:25 | 5.1 | Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs D. Sylvester, C. Hu, O.S. Nakagawa* and S.-Y. Oh* University of California, Berkeley, CA and *Hewlett-Packard, Palo Alto, CA |
| 3:50 | 5.2 | Stochastic Net Length Distributions for Global Interconnects in a Heterogeneous System-on-a Chip P. Zarkesh-Ha and J. Meindl Georgia Institute of Technology, Atlanta, GA |
| 4:15 | 5.3 | A Novel Air Gap Integration Scheme for Multi-Level Interconnects Using Self-Aligned Via Plugs T. Ueda, E. Tamaoka, K. Yamashita, N. Aoi and S. Mayumi Matsushita Electronics Corp., Kyoto, Japan |
| 4:40 | 5.4 | Low Resistance Dual Damascene Process by New Al Reflow Using Nb Liner J. Wada, Y. Oikawa, T. Katata, N. Nakamura and M.B. Anand Toshiba Corp., Yokohama, Japan |
SESSION 6: Capacitors for Giga DRAMs [TAPA II] | ||
| Chairpersons: | R. Mahnkopf, Siemens AG K. Shibahara, Hiroshima University | |
| 3:25 | 6.1 | Novel Poly-Si/Al2O3/Poly-Si Capacitor for High Density DRAMs Y.K. Kim, S.M. Lee, I.S. Park, C.S. Park, S.I. Lee and M.Y. Lee Samsung Electronics Co., Ltd., Kyungki-do, Korea |
| 3:50 | 6.2 | Dynamic Stressing Effects on Reliability of Strontium Titanate (SrTiO3) Thin Film Capacitors for High-Density Memory Applications T.-S. Chen, V. Balu, S. Katakam, J.-H. Lee, J.H. Han, R. Jones*, S. Gillespie* and J. Lee University of Texas, Austin, TX and *Motorola, Inc., Austin, TX |
| 4:15 | 6.3 | Properties of SrBi2Ta2O9 Thin Films Grown by MOCVD for High Density FeRAM Applications F. Hintermaier, B. Hendrix*, D. Desrochers*, J. Roeder*, C. Dehm, E. Fritsch, W. H”nlein, C. MazurŠ, N. Nagel, P. Thwaite, H. Wendt, T. Baum*, P. van Buskirk*, M. Schumacher**, M. Grossmann**, O. Lohse** and R. Waser** Siemens AG, Munich, Germany and *Advanced Technology Materials, Inc. Danbury, CT and **Aachen University of Technology, Aachen, Germany |
| 4:40 | 6.4 | Dielectric Breakdown, Reliability and Defect Density of (Ba0.7Sr0.3)TiO3 (BST) H. Reisinger, H. Wendt, G. Beitel and E. Fritsch Siemens Corporate Research and Development, Munich, Germany |
| SESSION 7: SRAM Technology [TAPA I] | ||
|---|---|---|
| Chairpersons: | C. Diaz, Hewlett-Packard Laboratories M. Kinugawa, Toshiba Corp. | |
| 8:30 | 7.1 | A Perfect Process Compatible 2.49um2 Embedded SRAM Cell Technology for 0.13u-Generation CMOS Logic LSIs Y. Sambonsugi, T. Maruyama*, K. Yano*, H. Sakaue*, H. Yamamoto*, E. Kawamura*, S. Ohkubo, Y. Tamura and T. Sugii Fujitsu Laboratories Ltd., Atsugi, Japan and *Fujitsu, Ltd., Kawasaki, Japan |
| 8:55 | 7.2 | Highly Scalable and Fully Logic Compatible SRAM Cell Technology with Metal Damascene Process and W Local Interconnect M. Inohara, H. Oyamatsu, Y. Unno*, Y. Fukaura, S. Goto, Y. Egi and M. Kinugawa Toshiba Corp., Yokohama, Japan and *Toshiba Micro-electronics Corp., Yokohama, Japan |
| 9:20 | 7.3 | A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device F. Nemati and J. Plummer Stanford University, Stanford, CA |
| 9:45 | 7.4 | A Novel 6.4um2 Full-CMOS SRAM Cell with Aspect Ratio of 0.63 in a High-Performance 0.25u- Generation CMOS Technology K.J. Kim, J.M. Youn, S.B. Kim, J.H. Kim, S.H. Hwang, K.T. Kim and Y.S. Shin Samsung Electronics Co., Ltd., Kyungki-do, Korea |
| 10:10 | Break | |
SESSION 8: Deep Sub-Micron MOSFETs [TAPA II] | ||
| Chairpersons: | B. Zetterlund, Digital Equipment Corp. N. Ouchi, Sony Corp. | |
| 8:30 | 8.1 | Channel Size Dependence of Dopant-Induced Threshold Voltage Fluctuation K. Takeuchi, NEC, Corp., Kanagawa, Japan |
| 8:55 | 8.2 | Buried Ultra-Low-Energy Gate Implants for Sub-0.25micron CMOS Technology J. Bevk, S.Kuehne*, H. Vaidya*, W. Mansfield, G. Hobler, et al., Bell Laboratories, Lucent Technologies, Murray Hill, NJ and *Bell Laboratories, Lucent Technologies, Orlando, FL |
| 9:20 | 8.3 | Ultra Low Power Supply Voltage (0.3V) Operation with Extreme High Speed Using Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Fast-Signal- Transmission Shallow Well A. Shibata, T. Matsuoka, S. Kakimoto, H. Kotaki, M. Nakano, K. Adachi, K. Ohta and N. Hashizume Sharp Corp., Nara, Japan |
| 9:45 | 8.4 | Channel Engineering of 0.13u nMOSFET for 1.0V CMOS Using Gate Poly-Si Oxidation and Laterally Profiled, Surface Concentrated Channel Technologies Y. Momiyama, H. Kurata, S. Ohkubo and T. Sugii Fujitsu Laboratories, Atsugi, Japan |
| 10:10 | Break | |
SESSION 9: Gbit DRAM Technology [TAPA I] | ||
| Chairpersons: | T.C. Chen, IBM T. Kunio, NEC Corp. | |
| 10:25 | 9.1 | An Evaluation of X-ray Lithography using a 0.175u (0.245 um2 cell area) 1Gb DRAM Technology R. Longo, S. Chaloux, A. Chen, A. Krasnoperova, S. Lee, G. Murphy, A. Thomas, C. Wasik, M. Weybright, G. Bronner, IBM Semiconductor R&D Center, Hopewell Junction, NY |
| 10:50 | 9.2 | A 0.15um KrF Lithography for 1Gb DRAM Product Using Highly Printable Patterns and Thin Resist Process T. Ozaki, T. Azuma, M. Itoh, D. Kawamura, S. Tanaka, Y. Ishibashi, S. Shiratake, S. Kyoh, T. Kondoh, S. Inoue, K. Tsuchida, Y. Kohyama and Y. Onishi Toshiba Corp., Yokohama, Japan |
| 11:15 | 9.3 | ARC for Sub-0.18u Logic and Gigabit DRAM Frontend and Backend Processes W. Lee, Q. He, A. Chatterjee, G. Xing, K. Brennan, A. Singh, E. Zielinski, M. Hanratty, S. Fang, D. Rogers, G. Dixit, D. Carter, J. Luttmer, R. Havemann and R. Chapman Texas Instru-ments, Dallas, TX |
| 11:40 | 9.4 | Channel Engineering Using B10H14 Ion Implantation for Low Vth and High SCE Immunity of Buried-Channel PMOSFETs in 4-Gbit DRAMs and Beyond T. Tanaka, H. Ogawa*, K. Goto, K. Itabashi*, T. Yamazaki*, J. Matsuo**, T. Sugii and I. Yamada** Fujitsu Labs, Ltd., Atsugi, Japan and *Fujitsu Ltd., Kawasaki, Japan and **Kyoto University, Kyoto, Japan |
| 12:05 | Lunch | |
SESSION 10: RF MOSFET Technology [TAPA II] | ||
| Chairpersons: | G. DiSanti, SGS-Thomson Microelectronics T.M. Liu, TSMC | |
| 10:25 | 10.1 | A 50-GHz 0.25um High-Energy Implanted BiCMOS (HEIBiC) Technology for Low Power High-Inte-gration Wireless Communication Systems Y.-F. Chyan, T. Ivanov, M. Carroll, W. Nagy, A.S. Chen and K.H. Lee Bell Laboratories, Lucent Technologies, Orlando, FL |
| 10:50 | 10.2 | CMOS RF Modeling for GHz Communication ICs J.-J. Ou, X. Jin, I. Ma, C. Hu and P. Gray University of California, Berkeley, CA |
| 11:15 | 10.3 | RF Noise in 1.5nm Gate Oxide MOSFETs and the Evaluation of the NMOS LNA Circuit Integrated on a Chip H.S. Momose, R. Fujimoto, S. Otaka, E. Morifuji, T. Ohguro, T. Yoshitomi, H. Kimijima, S. Nakamura, T. Morimoto, Y. Katsumata, H. Tanimoto and H. Iwai Toshiba Corp., Kawasaki, Japan |
| 11:40 | 10.4 | A Study of Self-Align Doped Channel Structure for Low Power and Low 1/f Noise Operation T. Yoshitomi, H. Kimijima, S. Ishizuka, Y. Miyahara, T. Ohguro, E. Morifuji, T. Morimoto, H.S. Momose, Y. Katsumata and H. Iwai Toshiba Corp., Kawasaki, Japan |
| 12:05 | Lunch | |
SESSION 11: Flash Memory Technology [TAPA I] | ||
| Chairpersons: | M. Chern, Atmel Corp. N. Ajika, Mitsubishi Electric Corp. | |
| 1:30 | 11.1 | A Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1Gbit Flash Memories Y. Takeuchi, K. Shimizu, K. Narita, E. Kamiya, T. Yaegashi, K. Amemiya and S. Aritome Toshiba Corp., Yokohama, Japan |
| 1:55 | 11.2 | A Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG T. Kitamura, M. Kawata, I. Honma, I. Yamamoto, S. Nishimoto and K. Oyama NEC Corp., Kanagawa, Japan |
| 2:20 | 11.3 | A Novel Step Stack NOR Cell for Low Voltage Flash S. Ogura, A. Hori*, J. Kato*, S. Odanaka*, K. Akamatsu*, M. Yamanaka*, M. Kojima** and H. Kotani** Halo LSI, Inc., Wappingers Falls, NY and *Matsushita Electronics Corp. and **Matsushita Electric Ind. Co. |
| 2:45 | 11.4 | A Novel Channel Boost Capacitance (CBC) Cell Technology with Low Program Disturbance Suitable for Fast Programming 4Gbit NAND Flash Memories S. Satoh, K. Shimizu, T. Tanaka, F. Arai, S. Aritome and R. Shirota, Toshiba Corp. Yokohama, Japan |
| 3:10 | Break | |
SESSION 12: SOI Technology [TAPA II] | ||
| Chairpersons: | G. Bomchil, France Telecom Y. Omura, Kansai University | |
| 1:30 | 12.1 | Comprehensive Study on AC Characteristics in SOI MOSFETs for Analog Applications Y.-C. Tseng, W.M. Huang*, D. Monk*, D. Diaz*, J. Ford* and J. Woo University of California, Los Angeles, CA and *Motorola, Inc., Mesa, AZ |
| 1:55 | 12.2 | A Dynamic Depletion SOI MOSFET Model for SPICE D. Sinitsky, S. Fung*, S. Tang, P. Su, M. Chan*, P. Ko* and C. Hu University of California, Berkeley, CA and *Hong Kong University of Science and Technology, Hong Kong, China |
| 2:20 | 12.3 | A 0.18u Fully Depleted CMOS on 30nm Thick SOI for Sub-1.0V Operation K. Imai, H. Onishi, K. Yamaguchi, K. Inoue, Y. Matsubara, A. Ono and T. Horiuchi NEC Corp., Kanagawa, Japan |
| 2:45 | 12.4 | Benefits of SiF3+ Implanted Titanium Silicides in Advanced CMOS Fabrication L. Wang, H. Tseng, S. Pozder, Motorola, Inc., Austin, TX |
| 3:10 | Break | |
SESSION 13: FeRAM Memory Technology [TAPA I] | ||
| Chairpersons: | R. Nowak, Applied Materials M. Ohkura, Hitachi, Ltd. | |
| 3:25 | 13.1 | A Highly Reliable 1T/1C Ferroelectric Memory D.-J. Jung, S.-Y. Lee, B.J. Koo, Y.-S. Hwang, D.-W. Shin, J. -W. Lee, Y. Chun, S.-H Shin, M.-H. Lee, H.-B. Park, S.-I. Lee, K. Kim and J.-G. Lee Samsung Electronics, Co., Kyungki-do, Korea |
| 3:50 | 13.2 | High Tolerance Operation of 1T/2C FeRAMs for the Variation of Cell Capacitors Characteristics N. Tanabe, S. Kobayashi, T. Miwa, K. Amanuma, H. Mori, N. Inoue, T. Takeuchi, S. Saitoh, Y. Hayashi, J. Yamada, H. Koike, H. Hada and T. Kunio NEC Corp., Kanagawa, Japan |
| 4:15 | 13.3 | A Scalable Single-Transistor/Single-Capacitor Memory Cell Structure Characterized by an Angled-Capacitor Layout for Megabit FeRAMs T. Kachi, K. Shoji, H. Yamashita*, T. Kisu*, K. Torii, T. Kumihashi, Y. Fujisaki and N. Yokoyama Hitachi Ltd., Kokubunji, Tokyo, Japan and *Hitachi ULSI Engineering Corp., Tokyo, Japan |
| 4:40 | 13.4 | Normally-off PLED (Planar Localised Electron Device) for Non-Volatile Memory, H. Mizuta, K. Nakazato, P. Piotrowicz, K. Itoh*, T. Teshima*, K. Yamaguchi* and T. Shimada* Hitachi Europe Ltd., Cambridge, UK and *Hitachi Ltd., Tokyo, Japan |
SESSION 14: Advanced Shallow Junction Technology [TAPA II] | ||
| Chairpersons: | Y. Taur, IBM S. Konaka, NTT Corp. | |
| 3:25 | 14.1 | Source/Drain Extension Scaling for 0.1um and Below Channel Length MOSFETs S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi, I. Post, S. Tyagi, S. Ahmed, S. Yang and M. Bohr Intel Corp., Hillsboro, OR |
| 3:50 | 14.2 | 33nm Ultra-Shallow Junction Technology by Oxygen-Free and Point-Defect Reduction Process S. Shishiguchi, A. Mineji, T. Yasunaga and S. Saito NEC Corp., Kanagawa, Japan |
| 4:15 | 14.3 | High Performance RF Characteristics of Raised Gate/Source/Drain CMOS with Co Salicide T. Ohguro, H. Naruse, H. Sugaya, S. Nakamura, E. Morifuji, H. Kimijima, T. Yoshitomi, T. Morimoto, H.S. Momose, Y. Katsumata and H. Iwai Toshiba Corp., Kawasaki, Japan |
| 4:40 | 14.4 | Direct Channel Length Determination of sub-100nm MOS Devices Using Scanning Capacitance Microscopy R. Kleiman, M. O'Malley, F. Baumann, J. Garno, W. Timp and G. Timp Bell Laboratories/Lucent Technologies, Murray Hill, NJ |
| RUMP SESSIONS | ||
|---|---|---|
| Technology and Circuits Joint Rump Session [Tapa III] | ||
| Organizers: | R. Havemann, Texas Instruments M. Kinugawa, Toshiba | |
| RJ1 | High Performance Technology for 1GHz Operation and Beyond - Architecture, Design and Device Solutions Technology: B. Zetterlund, DEC H. Iwai, Toshiba Circuits: S. Borkar, Intel Corp. Y. Oowaki, Toshiba Microprocessors and ASICs running at clock speeds in excess of 1 GHz are on the horizon. To achieve these speeds will require close coupling of technology, circuit implementation and architecture. Device technology continues on a well established scaling path. Interconnect technology is moving towards copper and low K dielectrics. Will this traditional scaling approach be able to meet the requirements? Will SOI be required? Currently, great emphasis is placed on controlling poly CD to maintain circuit functionality. Will new architectures and new circuit implementations extend this control to the interconnect? | |
Technology Rump Session [Honolulu I] | ||
| R2 | Lithography Technology Beyond ArF (sub 0.1æm) L. Van den hove, IMEC S. Matsui, Selete The end of optical lithography has long been (prematurely) forecasted, but it now appears that we may finally be running out of new wavelengths and other enhancements. There are numerous contenders to follow optical lithography, including X-ray, extreme UV, ion beam, and various electron beam techniques. This panel will discuss the benefits and challenges of the potential replacement technologies, as well as, possible further extensions of optical lithography. The panelists will describe the current state of the art in each of these technologies, and discuss and debate the probabilities for the technical and economic challenges to be overcome. | |
Technology Rump Session [Honolulu II] | ||
| R3 |
MOSFET Technology Beyond 0.1æm
R. Chapman , Texas Instruments T. Mogami , NEC Will transistors beyond 0.1æm be simple scaled versions of today's transistors? At what dimension could we need new technology - .08æm, 0.05æm, 0.03æm? Will metal gate replace salicided n+/p+ polysilicon gates? Can we scale SiO2 gate insulators as far as required, or will we need (thicker than SiO2) new high dielectric constant dielectrics for gate insulator to prevent gate tunneling? How are we going to obtain shallow low resistance junctions - will raised source drain be necessary? How will we limit short-channel effects - will we need double-gate or vertical transistor structures? Are there structures less sensitive to process control variability and intrinsic fluctuations? These points will be discussed and (hopefully) debated. | |
Technology Rump Session [Honolulu III] | ||
| R4 |
Copper Interconnect Technology Challenges
J. Ryan , IBM T. Kikkawa , NEC This rump session will address the technology challenges associated with the move to copper interconnects, such as the timeframe, key unit processes, dual damascene patterning methodologies, manufacturability issues, limitations to extendibility, and design implications. No discussion of interconnect technology extendibility would be complete without discussion of the integration of copper interconnects with dielectrics. New dielectric materials are expected to be introduced during the same timeframe as copper interconnects, in order to minimize wiring capacitance. This rump session should attempt to identify any special copper - low k integration issues, what type of dielectric structures will be needed, and generally discuss dielectric material candidates (e.g., important attributes, equipment directions). | |
| SESSION 15: VLSI Manufacturing [TAPA I] | |||
|---|---|---|---|
| Chairpersons: | M. Bohr, Intel Corp. T.M. Liu, TSMC | ||
| 8:30 | 15.1 | Excellent Process Control Technology for Highly Manufacturable and High Performance 0.18um CMOS LSIs T. Nakayama, T. Asamura, M. Kako, M. Murota, M. Matsumoto, Y. Washizu, K. Tomose, K. Kasai, Y. Okayama, K. Hashimoto, K. Ohuchi, K. Hattori, J. Shiozawa, H. Harakawa, F. Matsuoka and M. Kinugawa Toshiba Corp., Yokohama, Japan | |
| 8:55 | 15.2 | Optimization of a 0.18um 1.5V CMOS Technology to Achieve 15 ps Gate Delay I. Yang, P. Gilbert, C. Pettinato, S. Anderson, R. Woodruff, V. Misra, N. Bhat, K. Reid, T. Lii, C. Yuan, D. Dyer, D. O'Meara, S. Collins, H. De and S. Veeraraghavan Motorola, Inc., Austin, TX | |
| 9:20 | 15.3 | A Highly Manufacturable 0.25um Multiple-Vt Dual Gate Oxide CMOS Process for Logic/Embedded IC Foundry Technology M.H. Chang, J.K. Ting, J. Shy, L. Chen, C. Liu, J.Y. Wu, K.H. Pan, C.S. Hou, et al., TSMC, Taiwan, ROC | |
| 9:45 | 15.4 | A Manufacturable and Modular 0.25um CMOS Platform Technology P. Tsui, H. Chuang, N. Bhat, E. Travis, S. Chheda, J. Grant, P. Gilbert, P. Chen, S. Poon, A. Kaiser, et al., Motorola, Austin, TX | |
| 10:10 | Break | ||
SESSION 16: Reliability Technology I [TAPA III] | |||
| Chairpersons: | C. van der Poel, Philips Research Labs M. Ohkura, Hitachi, Ltd. | ||
| 8:30 | 16.1 | Electromigration of Submicron Damascene Copper Interconnects C. Ryu, K.W. Kwon, A. Loke, V. Dubin*, R. Kavari**, G. Ray** and S. Wong Stanford University, Stanford, CA and *Advanced Micro Devices, Sunnyvale, CA and **Hewlett-Packard Labs, Palo Alto, CA | |
| 8:55 | 16.2 | A New Prediction Method for Oxide Lifetime and Its Application to Study Dielectric Breakdown Mechanism K. Okada, H. Kubo, A. Ishinaga and K. Yoneda Matsushita Electronics Corp., Kyoto, Japan | |
| 9:20 | 16.3 | Performance and Reliability of Sub-100nm MOSFETs with Ultra Thin Direct Tunneling Gate Oxides Q. Xiang, G. Yeap, D. Bang, M. Song, K. Ahmed, E. Ibok and M. Lin Advanced Micro Devices, Inc., Sunnyvale, CA | |
| 9:45 | 16.4 | A New Degradation Scheme for Direct-Tunneling Ultrathin Gate Dielectric N. Kimizuka, T. Yamamoto and T. Mogami NEC Corp., Kanagawa, Japan | |
| 10:00 | Break | ||
SESSION 17: Deep Sub-Micron Patterning [TAPA I] | |||
| Chairpersons: | D. Kyser, Advanced Micro Devices H. Hanafusa, Sanyo Electric Co., Ltd. | ||
| 10:25 | 17.1 | CVD Photoresist Processes for Sub-0.18um Design Rules T. Weidman, D. Sugiarto, M. Nault, D. Mui, Z. Osborne, C. Lee* and J. Yang* Applied Materials, Santa Clara, CA and *Intel Corporation, Santa Clara, CA | |
| 10:50 | 17.2 | A Novel Resist and Post-Etch Residue Removal Process Using Ozonated Chemistries S. DeGendt, P. Snee, I. Cornelissen, M. Lux, R. Vos, P. Mertens, D. Knotter and M. Heyns IMEC, Leuven, Belgium | |
| 11:15 | 17.3 | A Statistical Gate CD Control Including OPC A. Misaka, A. Goda, S. Odanaka, S. Kobayashi and H. Watanabe Matsushita Electronics Corporation, Kyoto, Japan | |
| 11:40 | 17.4 | A Novel Etch Chemistry for Low-Damage Poly-Si Gate Patterning H. Richter, M. Aminpur, A. Wolff, R. Sorge and W.D. Rau Institute for Semiconductor Physics, Frankfurt, Germany | |
| 12:05 | Lunch | ||
SESSION 18: Hot Carriers [TAPA-III] | |||
| Chairpersons: | R. Rakkhit, LSI Logic J. Ida, Oki Electric Industry Co., Ltd. | ||
| 10:25 | 18.1 | A New Mode of Hot Carrier Degradation in 0.18um CMOS Technologies C.T. Liu, E.J. Lloyd, C.P. Chang, K. Cheung, J. Colonell, W. Lai, R. Liu, C. Pai, H. Vaidya and J. Clemens Bell Laboratories, Lucent Technologies, Murray Hill, NJ | |
| 10:50 | 18.2 | Temperature Dependence of Substrate Current and Hot Carrier-Induced Degradation at Low Drain Bias P. Aminzadeh, M. Alavi and D. Scharfetter Intel Corp., Hillsboro, OR | |
| 11:15 | 18.3 | Deuterium Process of CMOS Devices: New Phenomena and Dramatic Improvement Z. Chen, J. Lee, J. Lyding and K. Hess University of Illinois, Urbana, IL | |
| 11:40 | 18.4 | Limitation of Post-Metallization Annealing Due to Hydrogen Blocking Effect of Multilevel Interconnect S. Ito, K. Noguchi, T. Horiuchi and J. Clemens* NEC Corp., Kanagawa, Japan and *Bell Laboratories, Lucent Technology Inc., Murray Hill, NJ | |
| 12:05 | Lunch | ||
SESSION 19: Silicide and Gate Technology [Tapa I] | |||
| Chairpersons: | W. Lynch J. Ida, Oki Electric Industry Co., Ltd. | ||
| 1:30 | 19.1 | Highly-Reliable, Low-Resistivity bcc-Ta Gate MOS Technology Using Low-Damage Xe-Plasma Sputtering and Si-Encapsulated Silicidation Process K. Ino, T. Ushiki, K. Kawai, I. Ohshima, T. Shinohara and T. Ohmi Tohoku University, Sendai, Japan | |
| 1:55 | 19.2 | Highly Uniform Heteroepitaxy of Cobalt Silicide by Using Co-Ti Alloy for Sub-Quarter Micron Devices T. Iinuma, H. Akutsu, K. Ohuchi, K. Miyashita, Y. Toyoshima and K. Suguro, Toshiba Corp. Yokohama, Japan | |
| 2:20 | 19.3 | Optimized Poly-Si1-xGex-Gate Technology for Dual Gate CMOS Application W.C. Lee, T.J. King, and C. Hu University of California, Berkeley, CA | |
| 2:45 | 19.4 | Pure Ge Mid-Gap Gate Within an Industrial High Performance and Low Standby Current 0.18um CMOS Process J. Alieu, R. Gwoziecki, M. Paoli, T. Skotnicki, C. Hernandez, F. Martin, C. Mourrain, D. Bensahel, M. Basso*, J. Galvier and M. Haond* France Telecom, Meylan Cedex, France and *SGS-Thomson Microelectronics, Crolles, France | |
| 3:10 | Break | ||
SESSION 20: Reliability Technology II [Honolulu Suite] | |||
| Chairpersons: | J. Sansbury, Invox Technology T. Shibata, University of Tokyo | ||
| 1:30 | 20.1 | Microscopic and Statistical Approach to SILC Characteristics - Exponential Relation between Distributed Fowler Nordheim Coefficients and Its Physical Interpretation N. Tsuji, K. Sakakibara, N. Ajika and H. Miyoshi Mitsubishi Electric, Corp., Hyogo, Japan | |
| 1:55 | 20.2 | Gate-Oxide Degradation from Source/Drain (S/D) Boron Diffusion K. Cheung, C. Chang, J. Colonell, W.Y.C. Lai, C.T. Liu, R. Liu, C.S. Pai, C. Rafferty, H. Vaidya and J. Clemens Bell Laboratories, Lucent Technologies, Murray Hill, NJ | |
| 2:20 | 20.3 | Local Mechanical Stress Induced Defects for Ti and Co/Ti Silicidation in Sub-0.25um MOS-Technologies A. Steegen, K. Maex and I. DeWolf IMEC, Leuven, Belgium | |
| 2:45 | 20.4 | Impact on Soft Error Rate of Using Platinum Electrodes in 1 Gb DRAMs S.H. Yang, J. Seitchik, T. Aton and H. Shichijo Texas Instruments, Dallas, TX | |
| 3:10 | Lunch | ||
SESSION 21: Shallow Trench Isolation [Tapa I] | |||
| Chairpersons: | C. Osburn, North Carolina State Univ. S. Odanaka, Matsushita Electronics Corp. | ||
| 3:25 | 21.1 | Trench Transformation Technology Using Hydrogen Annealing for Realizing Highly Reliable Device Structure with Thin Dielectric Films T. Sato, I. Mizushima, J. Iba, M. Kito, Y. Takegawa, A. Sudo and Y. Tsunashima Toshiba Corp., Yokohama, Japan | |
| 3:50 | 21.2 | A New STI Process Based on Selective Oxide Deposition N. Elbel, Z. Gabric, W. Langheinrich* and B. Neureither Siemens AG, Munich, Germany and *SIMEC, Dresden, Germany | |
| 4:15 | 21.3 | A Shallow Trench Isolation with SiN Guard-Ring for Sub-Quarter Micron CMOS Technologies T. Ogura, T. Yamamoto, Y. Saito, Y. Hayashi and T. Mogami NEC Corp., Kanagawa, Japan | |
| 4:40 | 21.4 | Characterization and Elimination of Trench Dislocations J. Damiano, C. Subramanian, M. Gibson, Y. Feng, L. Zeng, J. Sebek, E. Deeters, C. Feng, T. McNelly, M. Blackwell, H. Nguyen, H. Tian, J. Scott, J. Zaman, C. Honcik, M. Miscione, K. Cox and J. Hayden Motorola, Austin, TX | |
SESSION 22: Advanced Gate Dielectrics [Honolulu Suite] | |||
| Chairpersons: | D. Huber, Wacker Siltronic E. Suzuki, Electrotechnical Laboratory | ||
| 3:25 | 22.1 | Stacked Gate Dielectrics with TaO for Future CMOS Technologies I. Kizilyalli, P. Roy, F. Baumann*, R. Huang, D. Hwang, C. Chacon, R. Irwin, Y. Ma, and G. Alers* Lucent Technologies, Bell Labs, Orlando, FL and *Murray Hill, NJ | |
| 3:50 | 22.2 | Highly Robust Ultra-Thin Gate Dielectric for Giga Scale Technology M. Khare, X.W. Wang, T.P. Ma, G.J. Cui*, T. Tamagawa*, B. Halpern* and J. Schmitt* Yale University, New Haven, CT and *Jet Process Corp., New Haven, CT | |
| 4:15 | 22.3 | Nitrogen Concentration Optimization for Down-Scaled CMOSFET with N2O-Based Oxyni-tride Process Y. Okayama, K. Kasai, T. Yamaguchi, A. Ooishi, M. Takayanagi-Takagi, F. Matsuoka and M. Kinugawa Toshiba Corp., Yokohama, Japan | |
| 4:40 | 22.4 | Ultra-thin, 1.0-30nm Gate Oxides for High Performance sub-100nm Technology T. Sorsch, W. Timp, F. Baumann, K. Bogart, T. Boone, V. Donnelly, M. Green, K. Evans-Lutterodt, C. Kim, S. Moccio, J. Rosamilia, J. Sapjeta, P. Silverman, B. Weir, and G. Timp Lucent Technologies/Bell Laboratories, Murray Hill, NJ | |
1998 VLSI TECHNOLOGY SYMPOSIUM COMMITTEE
Chairman:
Bill
Siu Intel Corporation
Co-Chairman:
Masao
Fukuma NEC
Program Chairman:
A.R.
Alvarez Cypress Semiconductor
Program Co-Chairman:
Masakazu
Kakumu Toshiba
Secretary:
Yuan Taur IBM
Takemitsu
Kunio NEC
Publications/Publicity:
Larry
Devito Analog Devices
Makoto
Ohkura Hitachi
Treasurer:
Richard
Jaeger Auburn University
Shinsuke
Konaka NTT
Local Arrangements:
Craig
Lage Motorola, Inc.
Yasuo
Inoue Mitsubishi Electric
Shoichiro Matsumoto Sanyo Electric
EXECUTIVE COMMITTEES
IEEE
Chairman:
James T.
Clemens Bell Labs, Lucent Technologies
Members:
Asad Abidi UCLA
Dirk
Bartelink Semiconductor Research Corporation
Richard
Chapman Texas Instruments
Gilbert
DeClerck IMEC
Youssef
El-Mansy Intel Corporation
Richard
Jaeger Auburn University
Nino
Masnari North Carolina State Univ.
Yoshi Nishi Texas
Instruments
Kevin
O'Connor Bell Labs, Lucent Technologies
Bill Siu Intel
Corp.
Charles
Sodini Massachusetts Institute of Technology
Peter
Verhofstadt Semiconductor Research Corporation
Ian Young Intel
Corp.
JSAP
Chairman:
Takuo
Sugano Toyo University
Members:
Shojiro
Asai Hitachi
Chun-Yen Chang National Chiao Tung University
Yutaka
Hayashi Sony
Hajime Ishikawa Fujitsu Labs
Choong-Ki
Kim KAIST
Susumu
Kohyama Toshiba
Jong-Gil Lee Samsung Electronics
Toshiaki
Masuhara Hitachi
Akihiko
Morino NEC
Tadashi
Nishimura Mitsubishi Electric
Toyoki Takemoto Matsushita Electric
Ken Takeya NTT
Fan-Churng
Tseng Vanguard International Semiconductor
TECHNICAL PROGRAM COMMITTEES
NORTH AMERICA/EUROPE
Chairman:
A.R.
Alvarez Cypress Semiconductor
Members:
Sanjay
Banerjee University of Texas
Mark Bohr Intel
Guillermo
Bomchil France Telecom
T.C. Chen IBM
G.C. Michael
Chern Atmel Corporation
Roger
DeKeersmaecker IMEC
Chuck
Dennison Micron Technology
Giorgio
DeSanti SGS-Thomson Micro.
Carlos
Diaz Hewlett-Packard Labs
Robert
Havemann Texas Instruments
Dieter
Huber Wacker Siltronic AG
David
Kyser Advanced Micro Devices
Craig
Lage Motorola, Inc.
Bill
Lynch Semiconductor Research Corporation
Reinhard
Mahnkopf Siemens AG
Carl Osburn N.
Carolina State University
C.S. Pai Lucent
Technologies, Bell Labs
Rajat Rakkhit LSI
Logic Corp.
Jim
Sansbury Invox Technology
Tom Seidel Genus
Corporation
Yuan Taur IBM
Carel van der
Poel Philips Research Labs
Simon
Wong Stanford University
Jason
Woo University of California
Bjorn
Zetterlund Digital Equipment Corporation
JAPAN/FAR EAST
Co-Chairman:
Masakazu
Kakumu Toshiba
Members:
Natsuo
Ajika Mitsubishi Electric
Hiroshi
Hanafusa Sanyo Electric
Chang-Gyu
Hwang Samsung Electronics
Jiro Ida Oki
Electric
Seiichiro
Kawamura Fujitsu
Masaaki
Kinugawa Toshiba
Shinsuke
Konaka NTT
Takemitsu
Kunio NEC
Teyin Mark
Liu TSMC
Shinji
Odanaka Matsushita Electric
Makoto
Ohkura Hitachi
Yasuhisa
Omura Kansai University
Shigeo
Onishi Sharp
Norikazu
Ouchi Sony
Kentaro
Shibahara Hiroshima University
Tadashi
Shibata University of Tokyo
Eiichi
Suzuki Electrotechnical Laboratory