You are cordially invited to attend the 1998 Symposium on VLSI Circuits, to be held on June 11th - 13th, 1998, at the Hilton Hawaiian Village in Honolulu, Hawaii.
This year the Symposium marks its 12th anniversary. The Symposium has established itself as a major international forum for presenting timely and important new developments in the VLSI and ULSI circuit design community. The scope of the Symposium has traditionally covered Analog, Digital, Memory and Signal Processing circuits contributed from both industry and universities from around the world. Preceding the Symposium on June 10th, a one-day short course on VLSI Circuits will be held. This short course will focus on Memory Design and Evolution. As has been traditional for a number of years, the Symposium on VLSI Circuits will be held for three days following the Symposium on VLSI Technology held at the same location.
This year sets a new record for participation in this Symposium. The technical program committees reviewed two hundred twenty one (221) papers from nineteen (19) countries around the world. Seventy (70) were selected for presentation. We hope that you agree that these papers disclose new and interesting circuit design concepts for memories, processors, communications circuits, and analog and digital signal processing. We expect the technical content of the program to make the Symposium a worthwhile event for every attendee.
In addition, we have invited four speakers to describe to you areas of interest to VLSI designers; designing clock distribution networks, deconstructing the semiconductor industry, digital television systems, and high-speed DRAM architecture movement.
In contrast to these formal talks, we have prepared four evening rump sessions on interesting and provocative subjects that offer you an opportunity to participate in discussions of interest with an international mix.
This booklet contains the advance program and forms for registration and hotel accommodations. Please try to complete and return these forms as soon as possible. While on-site registration will be available, early registration will facilitate the Symposium planning.
We look forward to meeting with you at the Symposium in Honolulu.
William Bidermann
Program Chairman
Masao Taguchi
Program Co-Chairman
| Technology and Circuits Joint Rump Session [Tapa III] | ||
|---|---|---|
| Organizers: | R. Havemann, Texas Instruments M. Kinugawa, Toshiba | |
| RJ1 | High Performance Technology for 1GHz Operation and Beyond - Architecture, Design and Device Solutions Technology: B. Zetterlund, DEC H. Iwai, Toshiba Circuits: S. Borkar, Intel Corp. Y. Oowaki, Toshiba Microprocessors and ASICs running at clock speeds in excess of 1 GHz are on the horizon. To achieve these speeds will require close coupling of technology, circuit implementation and architecture. Device technology continues on a well established scaling path. Interconnect technology is moving towards copper and low K dielectrics. Will this traditional scaling approach be able to meet the requirements? Will SOI be required? Currently, great emphasis is placed on controlling poly CD to maintain circuit functionality. Will new architectures and new circuit implementations extend this control to the interconnect? | |
| SESSION 1: Plenary Session I [Tapa II] | ||
|---|---|---|
| Chairpersons: |
William Bidermann, Chromatic Research Masao Taguchi, Fujitsu | |
| 8:30 | Welcome and Opening Remarks Ian Young, Intel Corporation Atsushi Iwata, Hiroshima University | |
| 8:45 | 1.1 | Designing the Best Clock Distribution Network
Phillip Restle and Alina Deutsch, IBM T.J. Watson Research Center |
| 9:30 | 1.2 |
Digital Television Systems
Yoshitaka Hashimoto, Sony Corporation |
| 10:15 | Break |
|
|
SESSION 2: High Speed DRAMs [Tapa II] | ||
| Chairpersons: | W. K. Loh, Texas Instruments C. Kim, Samsung Electronics | |
| 10:30 | 2.1 | 10-ns Row Cycle DRAM Using Temporal Data Storage Buffer Architecture S. Wakayama, K. Gotoh, M. Saito, H. Araki, T.S. Cheung, J. Ogawa and H. Tamura Fujitsu Laboratories Ltd., Kawasaki, Japan |
| 10:55 | 2.2 | Non-Precharged Bit-Line Sensing Scheme for High-Speed Low-Power DRAMs Y. Kato, N. Nakaya, T. Maeda, M. Higashiho, T. Yokoyama, Y. Sugo, F. Baba, Y. Takemae*, T. Miyabo* and S. Saito* Fujitsu VLSI Limited, Kasugai, Japan and *Fujitsu Limited, Kawasaki, Japan |
| 11:20 | 2.3 | Non-Complimentary Rewriting and Serial-Data Coding Scheme for Shared-Sense-Amplifier Open-Bit-Line DRAMS S. Utsugi, M. Hanyu, Y. Muramatsu and T. Sugibayashi NEC Corp., Kanagawa, Japan |
| 11:45 | 2.4 | Fast Cycle RAM (FCRAM); a 20-ns Random Row Access, Pipe-Lined Operating DRAM Y. Sato, T. Suzuki, T. Aikawa, S. Fujioka, W. Fujieda, H. Kobayashi, H. Ikeda, T. Nagasawa, A. Funyu, Y. Fujii, K. Kawasaki, M. Yamazaki and M. Taguchi Fujitsu Limited, Kawasaki, Japan |
| 12:10 | Lunch |
|
SESSION 3 [Tapa II] | ||
| Chairpersons: | B. Razavi, UCLA Y. Sugimoto, Chuo University | |
| 1:30 | 3.1 | A Low-Noise 900MHz VCO in 0.6u CMOS C.-H. Park and B. Kim KAIST, Taejon, Korea |
| 1:55 | 3.2 | A 1.9-GHz Si Bipolar Quadrature VCO with Fully-Integrated LC Tank T. Wakimoto and S. Konaka NTT Integrated Information & Energy Systems Labs, Kanagawa, Japan |
| 2:20 | 3.3 | Analysis and Optimization of Accumulation-Mode Varactor for RF ICs T. Soorapanth, C. Yue, D. Shaeffer, T. Lee and S. Wong Stanford University, Stanford, CA |
| 2:45 | 3.4 | A 30% Tuning Range Varactor Compatible with Future Scaled Technologies R. Castello, P. Erratico*, S. Manzini* and F. Svelto University of Pavia, Pavia, Italy and *SGS-Thomson, Milan, Italy |
| 3:10 | Break | |
SESSION 4: Low Power Digital Design [Tapa III] | ||
| Chairpersons: | A. Chandrakasan, MIT T. Kuroda, Toshiba Corp. | |
| 1:30 | 4.1 | A Low-Power IDCT Macrocell for MPEG2 MP@ML Exploiting Data Distribution Properties for Minimal Activity T. Xanthopoulos and A. Chandrakasan Massachusetts Institute of Technology, Cambridge, MA |
| 1:55 | 4.2 | A New Technique for Standby Leakage Reduction in High-Performance Circuits Y. Ye, S. Borkar and V. De Intel Corp., Hillsboro, OR |
| 2:20 | 4.3 | An Auto-Backgate-Controlled MT-CMOS Circuit H. Makino, Y. Tsujihashi, K. Nii, C. Morishima, Y. Hayakawa, T. Shimizu and T. Arakawa* Mitsubishi Electric Corp., Itami, Japan and *Tokushima Bunri University, Kagawa, Japan |
| 2:45 | 4.4 | A Novel Powering-Down Scheme for Low Vt CMOS Circuits K. Kumagai, H. Iwaki, H. Yoshida, H. Suzuki, T. Yamada and S. Kurosawa NEC Corp., Kanagawa, Japan |
| 3:10 | Break | |
SESSION 5: Oscillator and Wave Form Generators II [Tapa II] | ||
| Chairpersons: | B. Razavi, UCLA Y. Sugimoto, Chuo University | |
| 3:25 | 5.1 | Phase Noise in CMOS Differential LC Oscillators A. Hajimiri and T. Lee Stanford University, Stanford, CA |
| 3:50 | 5.2 | A 2V 900 MHz CMOS Phase-Locked Loop J.T. Wu, M.-J. Chen and C.-C. Hsu National Chiao-Tung University, Hsin-chu, Taiwan |
| 4:15 | 5.3 | A 0.8u CMOS 350 MHz Quadrature Direct Digital Frequency Synthesizer with Integrated D/A Converters A. Edman, A. Bj”rklid* and I. Soderquist* Link”ping University, Link”ping, Sweden and *SAAB Dynamics, Link”ping, Sweden |
| 4:40 | 5.4 | Quadrature Waveform Generator with Enhanced Performances F. Maloberti and M. Signorelli University of Pavia, Pavia, Italy |
SESSION 6: High Speed Memory Interface Control [Tapa III] | ||
| Chairpersons: | H. Kalter, IBM D.-K. Jeong, Seoul National University | |
| 3:25 | 6.1 | A Compact Ring Delay LIne for High Speed Synchronous DRAM S.-J. Jang, S.-H. Han, C.-S. Kim, Y.-H. Jun and H.-J. Yoo* LG Semicon Co., Ltd., Seoul, Korea and *KAIST, Daejon, Korea |
| 3:50 | 6.2 | An On-Chip Timing Adjuster with Sub-100-ps Resolution for a High-Speed DRAM Interface H. Noda, M. Aoki, H. Tanaka*, O. Nagashima and H. Aoki Hitachi, Ltd., Tokyo, Japan and *Hitachi ULSI Eng. Corp., Tokyo, Japan |
| 4:15 | 6.3 | 5GByte/s Data Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM T. Sato, Y. Nishio, T. Sugano and Y. Nakagome Hitachi, Ltd., Tokyo, Japan |
| 4:40 | 6.4 | A Delay-Locked Loop and 90-Degree Phase Shifter for 800Mbps Double Data Rate Memories T. Yoshimura, Y. Nakase, N. Watanabe, Y. Morooka, Y. Matsuda, M. Kumanoya and H. Hamano Mitsubishi Electric Corp., Itami, Japan |
| Circuits Rump Session [Honolulu I] | ||
|---|---|---|
| R1 |
Future of Scaling: Is Moore's Law All There Is?
A. Chandrakasan, MIT H. Onodera, Kyoto University Advances in process technology and circuit design techniques have enabled the exponential growth of transistor density and processor performance. Several challanges in deep sub-micron technology have to be addressed if this growth is to continue. Power dissipation, despite voltage scaling and other techniques, is quickly becoming a major limit to the scaling of performance. Fundamentally new techniques at all levels of the design will be required to deal with the power problem. Solutions are also required for dealing with interconnect, design complexity, clock distribution, etc. This panel will address these issues and critically analyze the fundamental and practical limits of scaling. | |
Circuits Rump Session [Honolulu II] | ||
| R2 |
Has SOI Finally Arrived?
C.T. Chuang, IBM Y. Ohtomo, NTT Corp. SOI has recently emerged as a serious contender for low power high- performance applications. However, its wide acceptance by the elec-tronics industry for mainstream applications is not apparent. This rump session brings together experts in the area of SOI device technology, logic, memory, and analog design to discuss the issues for SOI in mainstream VLSI applications. Topics to be addressed include:
| |
Circuits Rump Session [Honolulu III] | ||
| R3 |
Visions of Computers in the Year 2005
R. Allmon, DEC T. Sakurai, University of Tokyo Major advances in all technical disciplines of the computer industry are combining with a new global communication infrastructure to form a new era in computing. The panelists will discuss how this technology will enable new applications and how the user will gain access to computes and information. | |
| SESSION 7: Plenary Session II [Tapa II] | ||
|---|---|---|
| Chairpersons: | William Bidermann, Chromatic Research Masao Taguchi, Fujitsu, Ltd. | |
| 8:30 | 7.1 | Deconstructing the Semiconductor Industry George Zachary, Mohr Davidow Ventures |
| 9:15 | 7.2 | High-Speed DRAM Architecture Movement Hidemori Inukai, NEC Corp. |
| 10:00 | Break | |
SESSION 8: RF Receiver Circuits [Tapa I] | ||
| Chairpersons: | L. DeVito, Analog Devices K. Yamamoto, Oki Electric Industry Co. | |
| 10:20 | 8.1 | A CMOS RF-Receiver Front-End for 1GHz Applications F. Stubbe, S. Kishore, C. Hull and V. Della Torre Rockwell Semiconductor Systems, Newport Beach, CA |
| 10:45 | 8.2 | A 9mW 900MHz CMOS LNA with Mesh Arrayed MOSFETs G. Hayashi, H. Kimura, H. Simomura and A. Matsuzawa Matsushita Electric Ind., Co., Ltd., Osaka, Japan |
| 11:10 | 8.3 | A CMOS Variable Gain Amplifier for a Wideband Wireless Receiver S. Tadjpour, F. Behbahani and A. Abidi University of California, Los Angeles, CA |
| 11:35 | 8.4 | A 3V, 2.8mW CMOS ((-Modulator for GSM Applications T. Burger and Q. Huang Swiss Federal Institute of Technology, Zurich, Switzerland |
| 12:00 | Lunch | |
SESSION 9: DRAM Concepts [Tapa II] | ||
| Chairpersons: | D. Scott, Texas Instruments J. Ogawa, Fujitsu Labs., Ltd. | |
| 10:20 | 9.1 | A Precise On-Chip Voltage Generator for a Giga-Scale DRAM with a Negative
Word-Line Scheme H. Tanaka, M. Aoki*, T. Sakata*, S. Kimura*, N. Sakashita**, H. Hidaka**, T. Tachibana*** and K. Kimura* Hitachi ULSI Engineering Corp., Tokyo, Japan and *Hitachi Ltd., Tokyo, Japan and **Mitsubishi Electric Corp., Tokyo, Japan and ***Texas Instruments, Ltd., Tokyo, Japan |
| 10:45 | 9.2 | Multi-Gbit-Scale Partially Frozen (PF) NAND DRAM with SDRAM Compatible Interface T. Fujino and K. Arimoto Mitsubishi Electric Corp., Hyogo, Japan |
| 11:10 | 9.3 | A 5.3Gb/s 32Mb Embedded SDRAM Core with Slightly Boosting Scheme A. Yamazaki, T. Yamagata, M. Hatakenaka, A. Miyanishi, I. Hayashi, S. Tomishima, A. Mangyo, Y. Yukinari, T. Tatsumi, M. Matsumura, K. Arimoto and M. Yamada Mitsubishi Electric Corp., Hyogo, Japan |
| 11:35 | 9.4 | A 2.5V, 2.0GByte/s Packet-Based SDRAM with a 1.0Gbps/pin Interface C. Kim, K. Kyung, W. Jeong, J. Kim, B. Moon, S. Yim, J. Chai, J. Choi, C. Lee, K. Han, C. Park, H. Choi and S. Cho Samsung Electronics, Co., Ltd. |
| 12:00 | Lunch | |
SESSION 10: High Speed Circuit Techniques [Tapa III] | ||
| Chairpersons: | C. T. Chuang, IBM M. Yamashina, NEC Corp. | |
| 10:20 | 10.1 | Semi-Dynamic and Dynamic Flip-FLops with Embedded Logic F. Klass, Sun Microsystems, Inc., Palo Alto, CA |
| 10:45 | 10.2 | 1GHz Logic Circuits with Sense Amplifiers O. Takahashi, N. Aoki, J. Silberman and S. Dhong IBM, Austin, TX |
| 11:10 | 10.3 | Parallel Condition-Code Generating for High Frequency PowerPC Microprocessors J. Burns and K. Nowka IBM Austin Research Laboratory, Austin, TX |
| 11:35 | 10.4 | Accurate On-Chip Interconnect Evaluation: A Time Domain Technique K. Soumyanath, S. Borkar, C. Zhou and B. Bloechel Intel Corp., Hillsboro, OR |
| 12:00 | Lunch | |
SESSION 11: RF Transmitter Circuits [Tapa I] | ||
| Chairpersons: | G. Nasserbakht, Texas Instruments M. Ishikawa,DENSO | |
| 1:30 | 11.1 | A 3V GSM Baseband Transmitter C. Wong, LSI Logic Corporation, Milpitas, CA |
| 1:55 | 11.2 | A 2.7-V Dual-Frequency Single-Sideband Mixer T.P. Liu, Bell Laboratories, Lucent Technologies, Holmdel, NJ |
| 2:20 | 11.3 | A 900-MHz/1.8GHz CMOS Transmitter for Dual- Band Applications B. Razavi, University of California, Los Angeles, CA |
| 2:45 | 11.4 | Superharmonic Injection Locked Oscillators as Low Power Frequency Dividers H. Rategh and T. Lee Stanford University, Stanford, CA |
| 3:10 | Break | |
SESSION 12: Low Power SRAM [Tapa II] | ||
| Chairpersons: | H. Kalter, IBM H. Yamauchi, Matsushita Electric | |
| 1:30 | 12.1 | Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori and M. Horowitz Stanford University, Stanford, CA |
| 1:55 | 12.2 | Dynamic Leakage Cut-off Scheme for Low-Voltage SRAMs H. Kawaguchi, Y. Itaka and T. Sakurai University of Tokyo, Tokyo, Japan |
| 2:20 | 12.3 | A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme I. Fukushi, R. Sasagawa, M. Hamaminato, T. Izawa and S. Kawashima Fujitsu, Ltd., Kawasaki, Japan |
| 3:10 | Break | |
SESSION 13: Signal Processing [Tapa III] | ||
| Chairpersons: | S. Borkar, Intel Corp. M. Fujishima, University of Tokyo | |
| 1:30 | 13.1 | A 480MHz 11mW PR4 Viterbi Detector and Margin Circuit in 0.25u CMOS L. Thon, IBM Almaden Research Center, San Jose, CA |
| 1:55 | 13.2 | A CMOS 260Mbps Read Channel with EPRML Performance T. Conway, P. Quinlan, J. Spalding, D. Hitchcox*, I. Mehr**, D. Dalton** and K. McCall** Analog Devices, Limerick, Ireland and *Newbury, UK and **Wilmington, MA |
| 2:20 | 13.3 | An Analog DFE for Disk Drives Using a Mixed Signal Integrator M. Le, P. Hurst and K. Dyer University of California, Davis, CA |
| 2:45 | 13.4 | A New Contact Programming ROM Architecture for Digital Signal Processor H. Takahashi, S. Muramatsu and M. Itoigawa Texas Instruments Japan Ltd., Tokyo, Japan |
| 3:10 | Break | |
SESSION 14: Data Converters [Tapa I] | ||
| Chairpersons: | A. Abidi, University of California T. Miki, Mitsubishi Electric | |
| 3:25 | 14.1 | A 14-bit 5-MHz Digital-to-Analog Converter Using Multi-Bit Sigma-Delta Modulation, K. Falakshahi, C.K. Yang and B. Wooley Stanford University, Stanford, CA |
| 3:50 | 14.2 | A 1.5V, 10-Bit 14MS/s CMOS Pipeline Analog-to-Digital Converter, A. Abo and P. Gray, University of California, Berkeley, CA |
| 4.15 | 14.3 | A 2.5V 100MS/s 8bit ADC Using Pre-Linearization Input Buffer
and Level Up DAC/Subtractor, M. Sugawara, H. Yoshida, M. Mitsuishi, S. Nakamura, S. Nakaigawa, Y. Kunisaki and H. Suzuki, NEC Corporation, Kanagawa, Japan |
| 4:40 | 14.4 | A 4GHz Fourth-Order SiGe HBT Band Pass Sigma-Delta Modulator, W. Gao, J. Cherry and M. Snelgrove, Carleton University, Ottawa, Canada |
SESSION 15: High Speed SRAM [Tapa II] | ||
| Chairpersons: | D. Scott, Texas Instruments N. Lu, Etron Technology | |
| 3:25 | 15.1 | Bus Architecture for 600-MHz 4.5-Mb DDR SRAM, A. Kawasumi, A. Suzuki, H. Hatada, T. Kobayahsi, Y. Takeyama, O. Hirabayashi, T. Hamano and N. Otsuka, Toshiba Corp., Yokohama, Japan |
| 3:50 | 15.2 | A Write-Back Cache Memory Using Bit-Line Steal Technique, A. Miyoshi, H. Okuyama, S. Ozaki, T. Tsuji, K. Kaneko, S. Ogura and Y. Nishimichi, Matsushita Electric Industrial Co., Ltd., Kyoto, Japan |
| 4.15 | 15.3 | A 0.9-ns-access, 700-MHz SRAM Macro Using a Configurable
Organization Technique with an Automatic Timing
Adjuster, K. Ando, K. Higeta, Y. Fujimura, K. Mori, M. Nakayama, H. Nambu, K. Miyamoto* and K. Yamaguchi**, Hitachi, Ltd., Tokyo, Japan, *Hitachi Ltd., Kanagawa, Japan and **Hitachi ULSI Eng. Corp., Tokyo, Japan |
| 4:40 | 15.4 | A 2MB, 3.6GB/s Back-Side Bus Cache for an IA32 450 MHz Microprocessor, G. Taylor, T. Arabi, K. Hose, J. Jones, S. Kim, R. Kuppuswamy, R. Mooney, J. Price and A. Sarangi, Intel Corp., Hillsboro, OR |
SESSION 16: Communication Circuits [Tapa III] | ||
| Chairpersons: | I. Young, Intel Corp. K. Yamamoto, Oki Electric Industry Co. | |
| 3:25 | 16.1 | Front-End CMOS Chipset for Fiber-Based Gigabit Ethernet T. Yoon and B. Jalali* NuComm Corp. and *University of California, Los Angeles, CA |
| 3:50 | 16.2 | A 1 Gbit/s Full-Duplex CMOS Driver/Receiver for Twisted-Pair Data-Communication S. Gogaert and M. Steyaert Katholieke Universitaet, Leuven, Belgium |
| 4:15 | 16.3 | A 6Gbps CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock K. Nakamura, M. Fukaishi, H. Abiko, A. Matsumoto and M. Yotsuyanagi NEC Corp., Kanagawa, Japan |
| 4:40 | 16.4 | A 0.4u CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter R. Farjad-Rad, C.K. Yang, M. Horowitz and T. Lee Stanford University, Stanford, CA |
| SESSION 17: Image and Video Processing [Tapa I] | ||
|---|---|---|
| Chairpersons: | L. Mcllrath, Northeastern University M. Katakura, Sony Corp. | |
| 8:30 | 17.1 | Design and Fabrication of a High Dynamic Range Image Sensor in TFA Technology M. Bohm, T. Lule*, H. Fischer, J. Schulte, B. Schneider, S. Benthien*, F. Blecher, S. Coors, A. Eckhardt, H. Keller*, P. Rieve*, K. Seibel, M. Sommer* and J. Sterzel Universitaet GH, Siegen, Germany and *Silicon Vision GmbH, Siegen, Germany |
| 8:55 | 17.2 | A 1.5 GOPS Analog CMOS Array Processor with Integrated Optical Image Acquisition for Position Encoding Applications T. Blalock, R. Baumgartner and T. Hornak Hewlett-Packard Laboratories, Palo Alto, CA |
| 9:20 | 17.3 | A Comb Filter with Switched Capacitor Delay Lines for Analog Video Processor S. Dosho, H. Kurimoto, M. Ozasa, T. Okamoto, N. Yanagisawa and N. Tamagawa Matsushita Electric Ind. Co., Ltd., Osaka, Japan |
| 9:45 | Break | |
SESSION 18: PLL and High Speed Links [Tapa II] | ||
| Chairpersons: | H. Partovi, AMD N. Ishihara, NTT Corp. | |
| 8:30 | 18.1 | A Jitter and Data Duty Distortion Tolerated PLL Circuit for 156-Mbps Burst-Mode Transmission M. Sato, Y. Aoki, M. Baba, Y. Wakayama, N. Saikusa, M. Kayano and S. Murakami NEC, Corp., Kanagawa, Japan |
| 8:55 | 18.2 | A Phase-Locked Loop Clock Generator for a 1GHz Microprocessor D. Boerstler and K. Jenkins* IBM, Austin, TX and *IBM, Yorktown Height, NY |
| 9:20 | 18.3 | A Portable Digital DLL Architecture for CMOS Interface Circuits B. Garlepp, K. Donnelly, J. Kim, P. Chau, J. Zerbe, C. Huang, C. Tran, C. Portmann, D. Stark, Y. Chan, T. Lee* and M. Horowitz* Rambus, Inc., Mountain View, CA and *Stanford University, Stanford, CA |
| 9:45 | 18.4 | A 2Gb/s/pin CMOS Asymmetric Serial Link K.Y.K. Chang, W. Ellersick, S.T. Chuang, S. Sidiropoulos and M. Horowitz Stanford University, Stanford, CA |
| 10:10 | Break | |
SESSION 19: Analog Techniques [Tapa I] | ||
| Chairpersons: | P. Gray, University of California H. Onodera, Kyoto University | |
| 10:00 | 19.1 | A Five Stage Chopper Stabilized Instrumentation Amplifier Using Feedforward Compensation A. Thomsen, D. Kasha and W. Lee Cirrus Logic, Inc., Austin, TX |
| 10:25 | 19.2 | Experimental Results on Reduced Harmonic Distortion in Circuits with Correlated Double Sampling Y. Huang, G. Temes* and P. Ferguson, Jr.** Newport Microsystems, Inc., Irvine, CA and *Oregon State University, Corvallis, OR and **Analog Devices, Inc., Wilmington, MA |
| 10:50 | 19.3 | A CMOS Band-Gap Reference Circuit with Sub 1V Operation H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui Toshiba Corp., Yokohama, Japan |
| 11:15 | 19.4 | A Coding Scheme for Field-Powered RF IC Tag Systems S. Tanaka, T. Ishifuji, T. Saito, M. Shida and K. Nagai Hitachi, Ltd., Tokyo, Japan |
SESSION 20: Non-Volatile Memory [Tapa II] | ||
| Chairpersons: | M. Winston, Intel Corp. M. Hiraki, Hitachi, Ltd. | |
| 10:25 | 20.1 | A Negative Vth Cell Architecture for Highly Scalable, Excellently Noise Immune and Highly Reliable NAND Flash Memories K. Takeuchi, S. Satoh, T. Tanaka, K.I. Imamiya and K. Sakui Toshiba Corp., Yokohama, Japan |
| 10:50 | 20.2 | A Sophisticated Bit-by-Bit Verifying Scheme for NAND EEPROMs K. Sakui, K. Kanda, H. Nakamura, K.I. Imamiya and J. Miyamoto Toshiba Corp., Yokohama, Japan |
| 11:15 | 20.3 | A Self-Reference Read Scheme for a 1T/1C FeRAM J. Yamada, T. Miwa, H. Koike and H. Toyoshima NEC Corp., Kanagawa, Japan |
| 11:40 | 20.4 | A 42.5mm2 1Mb Nonvolatile Ferroelectric Memory Utilizing Advanced Architecture for Enhanced Reliability W. Kraus, L. Lehman, D. Wilson*, T. Yamazaki**, C. Ohno**, E. Nagai**, H. Yamazaki** and H. Suzuki** Ramtron International Corp. and *Corban Concepts, Inc., Colorado Springs, CO and **Fujitsu, Ltd., Kawasaki, Japan |