circuit

Welcome to the 1997 Symposium
on VLSI Circuits

You are cordially invited to attend the 1997 Symposium on VLSI Circuits, to be held on June 12-14th 1997, at the Rihga Royal Hotel Kyoto (previously named the Kyoto Grand Hotel) in Kyoto, Japan.
The Symposium, now in its eleventh year, has established itself as a major international forum for presenting and exchanging ideas on important new developments in the VLSI circuit design community. The scope of the Symposium has traditionally covered Analog, Digital, Memory, Signal Processing and Communications circuits with contributions from both industry and universities around the world.
Preceding the Symposium, on June 11th, a one-day Short Course on VLSI circuits will be held. This short course will focus on ``Challenges in Deep Submicron Design''.
As has been the tradition for a number of years, the Symposium on VLSI Circuits will be held for three days following the Symposium on VLSI Technology at the same location.
This year the program committees reviewed 127 papers submitted from 15 countries around the world. 53 papers were selected for presentation. We hope that you agree that these papers disclose new and interesting circuit design concepts for memories, processors, communication circuits, analog and signal processing. We expect for the technical content of the program to make the Symposium a fruitful event for every attendee.
In addition, we have invited four distinguished speakers to describe recent advances and new challenges in VLSI circuits and technology.
In contrast to these formal talks, we have prepared three evening rump sessions on interesting and provocative subjects that offer you an opportunity to participate in the discussions in international environments. There is also a joint rump session with the Symposium on VLSI Technology on the evening of June 11th, the day before the Symposium on VLSI Circuits begins.
This booklet contains the advance program together with forms for the Symposium registration and hotel reservations. Please try to complete and return these forms as soon as possible. While on-site registration will be available, pre-registration will facilitate Symposium planning.
We look forward to meeting with you at the Symposium in Kyoto.

Takayasu Sakurai	William Bidermann Program
Program Chairman	Program Co-Chairman

PROGRAM

Thursday, June 12

Session 1: Welcome and Plenary Session [Suzaku I, II]
Chairpersons:		T. Sakurai, Univ. of Tokyo W. Bidermann, Chromatic Research
8:30	1-1	Welcome and Opening Remarks T. Masuhara, Hitachi I . Young, Intel
8:45	1-2	Evolution of DVD by Advanced Semiconductor Technology (Invited) H. Nakatsuka, Toshiba, Japan
9:30	1-3	The 50th Anniversary of the Transistor-Historical Overview and Future Directions (Invited) J. Moll, Hewlett-Packard, USA
(Break 10:15-10:35)
Session 2: High-Speed Microprocessor Design [Suzaku I, II]
Chairpersons:		M. Yamashina, NEC I. Young, Intel
10:35	2-1	The Design of 300MIPS Microprocessor with a Full Associative TLB for Hand-Held PC OS K. Ishibashi, H. Higuchi, Y. Shimbo, F. Arakawa, O. Nishii, N. Nakagawa, H . Maejima, K. Osada, K. Norisue, R. Satomura, Aoki, Y. Shimazaki, K. Tanaka , T. Hattori, K. Shiozawa, K. Kudo, K. Uchiyama, S. Narita, J. Nishimoto, T. Nagano, S. Ikeda, K. Kuroda, T. Takeda and N. Hashimoto Hitachi and Hitachi ULSI Eng., Japan*
11:00	2-2	Issue Logic for a 600MHz Out-of-Order Execution Microprocessor J.A. Farrell and T.C. Fischer Digital Equipment, USA
11:25	2-3	A CMOS Temperature Sensor for Power PC{TM} RISC Microprocessors H. Sanchez, R. Philip, J. Alvarez and G. Gerosa Motorola, USA
11:50	2-4	A 4.5 Megabit, 560MHz, 4.5GByte/s High Bandwidth SRAM J. Greason, D. Buehler, J. Kolousek, Y.-G. Ng, K. Sarkez, P. Shay and A. Wa izman Intel, USA
(Lunch 12:15-13:45)
Session 3: High Speed and High Precision A/D Converters [Suzaku I]
Chairpersons:		M. Katakura, Sony L. DeVito, Analog Devices
13:45	3-1	A Delta-Sigma Pulse Width Modulator with Pulse Dithering R.S. Lewison and D.J. Allstot* Oregon State Univ. and Hewlett-Packard, USA*
14:10	3-2	1.2V, 16-bit Audio A/D Converter with Suppressed Latch Error Noise Y. Matsuya and J. Terada NTT, Japan
14:35	3-3	CMOS Charge-Transfer Preamplifier for Offset-Fluctuation Cancellation in Low-Power, High-Accuracy Comparators K. Kotani, T. Shibata and T. Ohmi Tohoku Univ., Japan
15:00	3-4	An 8-GSa/s 8-Bit ADC System K. Poulton, K.L. Knudsen, J. Kerley, J. Kang, J. Tani, E. Cornish and M. Va nGrouw Hewlett-Packard, USA
(Break 15:25-15:45)
Session 4: Emerging Digital Circuits [Suzaku II]
Chairpersons:		M. Fujishima, Univ. of Tokyo M. Afghahi, Intel
13:45	4-1	Self-Powered Low Power Signal Processing R. Amirtharajah and A. Chandrakasan MIT, USA
14:10	4-2	A 32x32-Bit Adiabatic Register File with Supply Clock Generator Y. Moon and D.-K. Jeong Seoul National Univ., Korea
14:35	4-3	Active Body-Bias SOI-CMOS Driver Circuits Y. Wada, K. Ueda, T. Hirota, Y. Hirano, K. Mashiko and H. Hamano Mitsubishi Electric, Japan
15:00	4-4	Pass-Transistor/CMOS Collaborated Logic: T he Best of Both Worlds S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H. Chikata, K. Rikino* and K. Seki Hitachi, Hitachi ULSI Eng. and *Hitachi Device Eng., Japan
(Break 15:25-15:45)
Session 5: Interface and Simulation Technique [Suzaku I]
Chairpersons:		H. Onodera, Kyoto Univ. P. Gray, UC Berkeley
15:45	5-1	High Speed Low EMI Digital Video Interface with Cable Deskewing and Transition Minimization Coding K. Lee, S. Kim, D.-K. Jeong, V.D. Costa, G. Kim and B. Kim* Seoul National Univ., Korea and Silicon Image, USA*
16:10	5-2	A Multi-Mode Digital Detector Readout for Solid-State Medical Imaging Detectors C.D. Boles, B.E. Boser, B.H. Hasegawa* and J.A. Heanue UC Berkeley and UC San Francisco, USA*
16:35	5-3	A Macroscopic Substrate Noise Model for Full Chip Mixed-Signal Design Verification M. Nagata and A. Iwata Hiroshima Univ., Japan
Session 6: High Speed Circuits [Suzaku II]
Chairpersons:		K. Ueda, Matsushita Electric H. Kalter, IBM
15:45	6-1	High Speed Adder Circuit Using Dummy Carry Method J. Mori, Y. Kondo and N. Ikumi Toshiba, Japan
16:10	6-2	A 500MHz 32-Word x 64-Bit 8-Port Self-Resetting CMOS Register File and Associated Dynamic-to-Static Latch W.H. Henkels, W. Hwang and R.V. Joshi IBM, USA
16:35	6-3	Precharged Cache Hit Logic with Flexible Timing Control W. Reohr, J. Navarro, Y.H. Chan, Y. Chan, M. Mayo, B. Curran, B. Krumm, A. Pelella, P.F. Lu, U. Bakhru, S. Kowalczyk, J. Rawlins, S. Carey and P. Wu IBM, USA

20:00 Rump Session:

R-1	1 GHz and Beyond - PLL and Clock Distribution
	Moderators:	N. Ishihara, NTT M. Afghahi, Intel
	The speed of the LSIs used in RISC processors and for synchronous memory has reached as high as several hundred MHz using on-chip PLLs and precise clock distribution technology. In the near future, will it be possible to exceed 1 GHz easily? Will this require break through technologies or not? Panelists will discuss solutions to the problems associated with the PLL structure, clock distribution techniques, power saving techniques, design tools, LSI chip mounting and testing, and try to predict when the speed will exceed 1GHz and what will limit the speed in the future.
R-2	Competing Architectures and Cell Technologies for High Performance DRAMs
	Moderators:	M. Taguchi, Fujitsu W. K. Loh, Texas Instruments
	Innovative technologies for reducing the Processor to Main Memory bandwidth bottleneck such as Double Data Rate (DDR) SDRAM and high-speed packet based architectures like RAMBUS or SynchLink will propel the industry to several Gigabyte/second data transfer rates. However, the core DRAM array remains fundamentally slow despite multi-bank segmentation methods. Several aspects such as reduction of internal operating voltage or cosmic ray events impose limits on minimum stored charge to sense margins. Internally ``boosted'' level continue to place constraints on gate oxide thickness due to maximum allowable e-fields. Alternative cell technologies like ferroelectric and high-K dielectric storage cells are in or near production. Multi-level storage schemes or NAND-type cells are also proposed and are under investigation. Stacked capacitor technology seems to be dominant but trench technology now again draws attention for RAM and Logic application capability. This panel will discuss the impact of these technologies on future DRAM devices for tomorrow's computers using today's innovations.
R-3	Will the Single-Chip RF Transceiver Dominate in the Range of 1 to 2GHz?
	Moderators:	T. Tsukahara, NTT A. A. Abidi, UC Los Angeles
	Is it worth striving for very high levels of integration, in terms of the final cost and performance? Integrated transceiver chips are large, with many inductors and large capacitors integrated with the active devices. Since small level RF and large level baseband signals are processed on the same chip, are crosstalk issues in a Si substrate still serious? Will the evolution of RF transceivers architectures to direct-conversion or quasi-IF configurations give true single-chip RF transceivers which have only RF and baseband ports, and power supplies?
Joint Rump Session with Technology:
	*This session will be held at the technology rump session on June 11
	Merged Logic and DRAM
	Circuit Moderators/Organizers:
		C. Kim, Samsung Electronics D. Scott, Texas Instruments
	Technology Moderators/Organizers:
		M. Yamawaki, Mitsubishi Electric S. Stiffler, IBM
	Do merged logic and DRAM integrated circuits have a viable future ? The issues involved relate to performance, process complexity, testing, manufacturing and even the culture of the technical community. We will discuss the types of application that may be suitable for merged DRAM and logic integrated circuits. Further we will pose the challenge of how these products can be tested within the constraints already imposed by pure logic and DRAM implementations.

Friday, June 13

Session 7: Plenary Session II [Shunju I, II]
Chairpersons:		T. Sakurai, Univ. of Tokyo W. Bidermann, Chromatic Research
8:30	7-1	Technology Innovations in Mobile Computers(Invited) K. Ishida, IBM Japan, Japan
9:15	7-2	Designing High Speed Microprocessors(Invited) P. Gronowski, Digital Equipment, USA
(Break 10:00-10:20)
Session 8: Merged DRAM and Logic [Shunju I, II]
Chairpersons:		C. Kim, Samsung W. K. Loh, Texas Instruments
10:20	8-1	An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe and M. Yamashina NEC, Japan
10:45	8-2	A Pixel-Parallel Image Processor Using Logic Pitch-Matched to Dynamic Memory J.C. Gealow and C.G. Sodini MIT, USA
11:10	8-3	An Access-Sequence Control Scheme to Enhance Random Access Performance of Embedded DRAMs K. Ayukawa, T. Watanabe and S. Narita Hitachi, Japan
(Lunch 11:35-13:15)
Session 9: Flash Memories [Shunju I]
Chairpersons:		K. Nakahara, Sharp C. Kuo, Motorola
13:15	9-1	Floating-Well Charge Pump Circuits for Sub -2.0V Single Power Supply Flash Memories K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung and K.-D. Suh Samsung Electronics, Korea
13:40	9-2	Circuit Technologies for a Single-1.8V Flash Memory T. Tanzawa, T. Tanaka, K. Takeuchi and H. Nakamura Toshiba, Japan
14:05	9-3	A 3.4-Mbyte/sec Programming 3-Level NAND Flash Memory Saving 40% Die Size Per Bit T. Tanaka, T. Tanzawa and K. Takeuchi Toshiba, Japan
14:30	9-4	A Multi-Page Cell Architecture for High-Speed Programming Multi-Level NAND Flash Memories K. Takeuchi, T. Tanaka and T. Tanzawa Toshiba, Japan
(Break 14:55-15:15)
Session 10: Data Communication Circuits [Shunju II]
Chairpersons:		N. Ishihara, NTT T. H. Meng, Stanford Univ.
13:15	10-1	A 2.4-Gb/s CMOS Clock Recovering 1:8 Demultiplexer M. Soda, H. Tezuka, S. Shioiri, A. Tanabe, A. Furukawa, M. Togo, T. Tamura and K. Yoshida NEC, Japan
13:40	10-2	A 0.6um CMOS 4Gb/s Transceiver with Data Recovery Using Oversampling C.-K.K. Yang, R. Farjad-Rad and M. Horowitz Stanford Univ., USA
14:05	10-3	An 11.8-GHz 31-mW CMOS Frequency Divider M. Kurisu, M. Nishikawa, H. Asazawa, A. Tanabe, M. Togo and A.Furukawa NEC, Japan
14:30	10-4	A Phase Interpolation Direct Digital Synthesizer with a Digitally Controlled Delay Generator H. Nosaka, T. Nakagawa and A. Yamagishi NTT, Japan
(Break 14:55-15:15)
Session 11: SRAMs and Non-Volatile Memories [Shunju I]
Chairpersons:		K. Mashiko, Mitsubishi Electric M. Horowitz, Stanford Univ.
15:15	11-1	A Charge Transfer Amplifier and an Encoded Bus Architecture for Low Power SRAM S. Kawashima, T. Mori, R. Sasagawa, M. Hamaminato, S. Wakayama, K Sukegawa* and I. Fukushi Fujitsu Labs. and Fujitsu, Japan*
15:40	11-2	A Hierarchical Sensing Scheme(HSS) of High-Density and Low-Voltage Operation SRAMs Y. Haraguchi, T. Wada and Y. Arita Mitsubishi Electric, Japan
16:05	11-3	Low Supply Voltage CMOS Charge Pumps J.-T. Wu and K.-L. Chang* National Chiao Tung Univ. and Macronix International, Taiwan*
16:30	11-4	High-Density Chain Ferroelectric Random-Access Memory (CFRAM) D. Takashima, I. Kunishima, M. Noguchi and S. Takagi Toshiba, Japan
(Dinner 18:00-20:00)
Session 12: RF Circuits [Shunju II]
Chairpersons:		Y. Sugimoto, Chuo Univ. G. Nasserbakht, Texas Instruments
15:15	12-1	On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's C.P. Yue and S.S. Wong Stanford Univ., USA
15:40	12-2	A 2.7 Volt CMOS Broadband Low Noise Amplifier J. Janssens, M. Steyaert and H. Miyakawa* Katholieke Univ. Leuven, Belgium and Toshiba, Japan*
16:05	12-3	A Very Low Offset 1.9-GHz Si Mixer for Direct Conversion Receivers S. Otaka, T. Yamaji, R. Fujimoto and H. Tanimoto Toshiba, Japan
16:30	12-4	A 2V 1.9GHz Si Down-Mixer with LC Phase Shifter H. Komurasaki, H. Sato, N. Sasaki and T. Miki Mitsubishi Electric, Japan
16:55	12-5	A Linearization Technique for CMOS RF Power Amplifiers S. Tanaka, F. Behbahani and A.A. Abidi UC Los Angeles, USA
(Dinner 18:00 - 20:00)

Saturday, June 14