• NAND Flash Technology and Chip Design - Instructor: Fujio Masuoka, Tohoku University, Japan
• NVRAM Technology, NOR Flash Design and Multi-Level Flash - Instructor: Stefan Lai, Intel Corporation, Santa Clara, CA
• Non-Volatile Memory Based on Solid State Mass Storage Technologies - Instructor: Daniel Guterman, SunDisk Corporation, Santa Clara, CA
• Embedded FLASH: Application, Technology and Design - Instructor: Clinton Kuo, Motorola, Austin, TX

• Portable Technologies: A System Perspective, Instructor: Erik P. Harris, IBM Watson Research Center, Yorktown Heights, NY
• Low-Power Baseband Electronics - Instructor: Akira Matsuzawa, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
• Low Power RF Technology and Design - Instructor: William R. Eisenstadt, University of Florida, Gainesville, FL
• Low Power Display Technology for Portable Systems - Instructor: Alan Lewis, Xerox PARC, Palo Alto, CA

• Consumer Electronics as the Technology Driver, Yoshitaka Hashimoto, Sony Corporation
• Smart Power Technology and the Evolution from Protective Umbrella to Complete System, Bruno Murari, SGS-Thomson Microelectronics
• CMOS Image Sensor: Electronic Camera on a Chip, Eric Fossum, NASA Jet Propulsion Laboratory

• Statistical Variation of NMOSFET Hot-Carrier Lifetime and its Impact on Digital Circuit Reliability
• Hot-Carrier-Induced Gate Capacitance Variation and Its Impact on DRAM Circuit Functionality
• Oxide-Field Dependence of the NMOS Hot-Carrier Degradation Rate and Its Impact on AC-Lifetime Prediction
• Accurate Measurements for Lateral Distribution of Interface Traps by Charge Pumping and Capacitance Methods
• LDD Charge Pumping - Direct Measurement of Interface States in the Overlap Region
• A Comparative Study of Hot-Carrier Induced Light Emission and Degradation in Bulk and SOI MOSFETs

Session 3: Integrated Circuits - Low Voltage/Low Power CMOS

• Reducing Operating Voltage from 3,2, to 1 Volt and Below - Challenges and Guidelines for Possible Solutions (Invited Paper)
• TFSOI CMOS Technology for Sub-1V Microcontroller Circuits
• Optimization of Quarter Micron MOSFETs For Low Voltage/Low Power Applications
• Intra-Die Device Parameter Variations and Their Impact on Digital CMOS Gates at Low Supply Voltages
• Reversal of Temperature Dependence of Integrated Circuits Operating at Very Low Voltages
• Discussion Session: Power/Voltage: How Low is Low?

Session 4: Modeling and Simulation - Process Modeling

• Ion Implantation and Transient Enhanced Diffusion (Invited Paper)
• Modeling Arsenic Activation and Diffusion During Furnace and Rapid Thermal Annealing
• Physically Based Modeling of Boron Diffusion in Thin Gate Oxides: Effects of F, H2, N, Oxide Thickness and Injected Si Interstitials
• 3D Modeling of Sputter and Reflow Processes for Interconnect Metals
• A Sputter Equipment Simulation System Including Molecular Dynamical Target Atom Scattering Model
• Three Dimensional PVD Virtual Reactor for VLSI Metallization
• Physical Etching/Deposition Simulation with Collision-Free Boundary Movement
• Simulation Approach for Achieving Configuration Independent Poly-Silicon Gate Etching

Session 5: Device Interconnect Technology - Advanced Memory Dielectrics

• Ta2O5 Capacitors' Dielectrics Material for Giga-Bit DRAM (Invited Paper)
• Novel Stacked Capacitor Technology for 1Gbit DRAMS with CVD-(Ba,Sr)TiO3 Thin Films on a Thick Storage Node of Ru
• An ECR MOCVD (Ba,Sr)TiO3 Based Stacked Capacitor Technology with RuO2/Ru/TiNTiSix Storage Nodes for Gbit-Scale DRAMs
• Effects of Scaling Thickness and Effective Doping Level on the Ferroelectric Thin Film Capacitor Memory Operation
• Characteristics of the PZT Thin Film Device Fabricated on the Single Grain
• Discussion Session

Session 6: Emerging Technologies

• New Generation MOS Controlled Power Devices and Their Applications (Invited Paper)
• Integrated Inductors for Low Cost Electronic Packages (Invited Paper)
• Electronic Sensing of the Taste of Beer and Other Foodstuffs (Invited Paper)

Session 7: Detectors, Sensors and Displays - Image Sensors

• High Resolution Tri-Linear Colour TDI CCD Image Sensor with Programmable Responsivity Gain
• An mK x nK Modular Image Sensor Design
• Optical Limitation to Cell Size Reduction in IT-CCD Image Sensors
• Characterization of Metal Contaminiation in CCD Image Sensors
• CCD-based Sensor Array for Magnetic Pattern Recognition
• A Fingerprint Opto-Detector Using Lateral Bipolar Phototransistors in a Standard CMOS Process
• A Solid-State Imager Joined to an Avalanche Multiplier Film with Micro-bump Electrodes

Session 8: Quantum Electronics and Compound Semiconductor Devices - Advanced Field Effect Transistors

• 11.5V-Operation GaAs Spike-Gate Power FET with 65% Power-Added Efficiency
• 1.2V Operation 1.1W Heterojunction FET for Portable Radio Applications
• High-Efficiency Dual-Gate InGaAs Pseudomorphic HEMTs for High Power Amplifiers Using Single-Voltage Supply
• Ultra-High-Speed InAlAs/InGaAs HEMT ICs Using pn-Level-Shift Diodes
• 0.1-um p+ -GaAs Gate HJFETs with ft=121 GHz Fabricated using All Dry-etching and Selective MOMBE Growth
• A New Physical Model for the Kink Effect on InAlAs/InGa/As HEMTs
• High-Transconductance Normally-Off GaN MODFETs
• Discussion Session

Session 9: Vacuum Electronics - Microwave Tubes

• Application of the "Klevafella" Permanent Magnet Focusing System to Linear Beam Microwave Tubes
• A CHI Wiggler Ubitron Amplifier Experiment: Wiggler Characterization
• The Development of High Frequency, Megawatt Gyrotrons for ITER
• Window-Temperature Measurements on a High-Power Gyrotron with an Internal, Quasi-Optical Converter
• Design of Two Low Voltage, Axially-Modulated, Cusp-Injected Gyrotron Amplifier Experiments
• Stable 200kW Second-Harmonic Gyro-TWT Amplifier Operation
• Initial Operation of a 100MW Fundamental Frequency Gyroklystron

• Interconnect Scaling - The Real Limiter to High Performance ULSI (Invited Paper)
• A Scaling Scheme for Interconnect in Deep-Submicron Processes
• Interconnect Capacitances, Crosstalk, and Signal Delay in Vertically Integrated Circuits
• Discussion Session
• Excellent Electro/Stress-Migration-Resistance Surface-Silicide Passivated Giant-Grain Cu-Mg Alloy Interconnect Technology for Giga Scale Integration (GSI)
• Low Temperature, Low Resistivity Sub-Half Micron Via/Interconnect Structure Using Reaction of Al-Alloys and Germane

Session 11: Integrated Circuits - Flash Memory Technology

• A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256Mbit and 1Gbit Flash Memories
• A New Cell Structure for Sub-Quarter Micron High Density Flash Memory
• Multi-Level Flash/EPROM Memories: New Self-Convergent Programming Methods for Low-Voltage Applications
• A Novel Side-Wall Transfer-Transistor Cell (SWATT Cell) for Multi-level NAND EEPROMs
• Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-Channel Cell
• Substrate-Current-Induced Hot Electron (SCIHE) Injection: A New Convergence Scheme for Flash Memory
• Discussion Session: Flash Memory Cell Scaling Issues for 256Mbit Generation and Beyond

Session 12: Modeling and Simulation - Hot Carrier Effects and Monte Carlo Simulation

• The Numerical Simulation of Substrate and Gate Currents in MOS and EPROMs
• Characterization and Modeling of Hot-Carrier Luminescence in Silicon n+/n/n+ Devices
• New Monte Carlo Simulation for Polystalline Silicon Thin-Film Transistor
• Hot Carrier Effects in Short MOSFETs at Low Applied Voltages
• Monte Carlo Study of Sub-Band-Gap Impact Ionization in Silicon Field-Effect Transistors
• Discussion Session

Session 13: CMOS Devices and Reliability - Plasma Damage and Gate Oxide Reliability

• Role of Temperature in Process-Induced Charging Damage in Sub-micron CMOS Transistors
• High Density Plasma Etch Induced Damage to Thin Gate Oxide
• Effects of Oxide Exposure, Photoresist and Dopant Activation on the Plasma Damage Immunity of Ultrathin Oxides and Oxynitrides
• A New Gate Oxide Lifetime Prediction Method Using Cumulative Damage Law and Its Applications to Plasma-Damaged Oxides
• The Impact of Nitrogen Profile Engineering on Ultra-Thin Nitrided Oxide Films for Dual-Gate CMOS ULSI
• Short Channel Enhanced Degradation During Discharge of Flash EEPROM Memory Cell

Session 14: Solid State Devices - ESD Protection, Discrete Power and Bipolar Devices

• Bipolar SCR ESD Protection Circuit for High Speed Submicron Bipolar/BiCMOS Circuits
• A Hot-Carrier Triggered SCR for Smart Power Bus ESD Protection
• Efficient NPN Operation in High Voltage NMOSFET for ESD Robustness
• A Planar MOS-Gated AC Switch Structure
• High Power 4H-SiC Static Induction Transistors
• Correlation of Low-Frequency Noise and Emitter-Base Reverse-Bias Stress in Epitaxial Si- and SiGe-base Bipolar Transistors

Session 15: Quantum Electronics and Compound Semiconductor Devices - Quantum and Novel Devices

• Comparison of Experimental and Theoretical Results of Room Temperature Operated Single Electron Transistor Made by STM/AFM Nano-Oxidation Process
• Single Hole Silicon Quantum Dot Transistors for Complementary CMOS Circuits
• Electron Transport Properties in InAs Self-Assembled Quantum Dot HEMTs
• A Novel Semimetallic Quantum Well FET
• Novel Current-Voltage Characteristics in an InP-Based High Electron Mobility Resonant-Tunneling Transistor and their Circuit Applications
• In-Situ Ga2O3 Process for GaAs Inversion/Accumulation Device and Surface Passivation Applications

Session 16: Vacuum Electronics - Field Emitter Arrays and Photocathodes

• Field-Emitter-Array Development for Microwave Applications
• Tower Structure Si Field Emitter Arrays with Large Emission Current
• A Robust Gated-Field-Emission Triode
• Scaling-down of Cone-like Field Emitter Using LOCOS
• Volcano-Shaped Field Emitters for Large Area Displays
• High-Performance Negative Electron Affinity Photocathodes for High Resolution Electron Beam Lithography and Metrology

• A Scaled 1.8V,0.18 m Gate Length CMOS Technology: Device Design and Reliability Considerations
• Device Drive Current Degradation Observed with Retrograde Channel Profiles
• Reverse Short Channel Effect and Channel Length Dependence of Boron Penetration in PMOSFETs
• The Effect of Source/Drain Processing on the Reverse Short Channel Effect of Deep Sub-Micron Bulk and SOI NMOSFETs
• A 0.1 m Inverted-Sidewall Recessed-Channel (ISRC) NMOSFET for High Performance and Reliability
• Performance and Reliability Optimization of Ultra Short Channel CMOS Device for Giga-bit DRAM Application
• A High Performance 0.1 m MOSFET with Asymmetric Channel Profile

Session 18: Device Interconnect Technology - Advanced Silicide and Metallization Technologies

• A New Cobalt Salicide Technology for 0.15 m CMOS Using High-Temperature Sputtering and In-Situ Vacuum Annealing
• Leakage Mechanism and Optimized Conditions of Co Salicide Process for Deep-submicron CMOS Devices
• Nitrogen-Doped Nickel Monosilicide Technique for Deep Submicron CMOS Salicide
• Novel Contamination Restrained Silicidation Processing Using Load-Lock LPCVD-Films and Lightly Doped Deep Drain (LD3) Structure for Deep Submicron Dual Gate CMOS
• A Comparative Study of CVD TiN and CVD IaN Diffusion Barriers for Copper Interconnection
• Completely Planarized W Plugs Using MnO2 CMP
• In Situ CMP Monitoring Technique for Multi-layer Interconnection -Fully Planarized Four-Level Interconnection with Stacked Vias Using CMP of Selective CVD-A1 and Insulator and its Application to Quarter Micron Gate Array LSIs

Session 19: Modeling and Simulation - Back-End Process Modeling

• CMOS Process Design for Minimization of IC Power Consumption Using TCAD (Invited Paper)
• The Implications of Self-Consistent Current Density Design Guidelines Comprehending Electromigration and Joule Heating on Interconnect Technology Evolution
• Thermal Analysis of Vertically Integrated Circuits
• Simulation and Modeling of the Effect of Substrate Conductivity on Coupling Inductance
• "NET-AN" a Full Three-Dimensional Parasitic Interconnect Distributed RLC Extractor for Large Full Chip Scale Applications
• Using a Statistical Metrology Framework to Identify Random and Systematic Sources of Intra-Die ILD Thickness Variation for CMP Processes
• Finite Element Optimization of a MOSFET Structure: The Role of Interlayer Material for Residual Stress Reduction

Session 20: Solid State Devices - Novel Devices and Techniques

• Si/SiG High-Speed Field-Effect Transistors (Invited Paper)
• Novel Poly-Si-Capped Poly-Si1-XGex Thin-Film Transistor
• Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs
• Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage
• Impact of Coulomb Blockade on Low-Charge Limit of Memory Device
• Reference Voltages and Their Stress-Induced Changes in Thin Film Transistors as Determined by Charge Pumping
• Silicon Film Thickness and Material Dependence of "Reverse Short Channel Effect" for SOI NMOSFETs

Session 21: Integrated Circuits - ESD and Other Specialized Structures

• A Novel On-Chip Electrostatic Discharge (ESD) Protection for Beyond 500MHz DRAM
• ESD Protection for Deep-Submicron CMOS Technology Using Gate-Couple CMOS-Trigger Lateral SCR Structure
• Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes
• On-State Reliability of Amorphous Silicon Antifuse
• A Neuron MOS Transistor-Based Multiplier Cell

Session 22: Quantum Electronics and Compound Semiconductor Devices - OptoElectronics

• Novel Components for Wavelength Division Multiplexed Systems Based on Monolithic Multiplexer/Amplifier Integration (Invited Paper)
• Low-Noise 650nm-Band AlGaInP Visible Lasers with Highly-Doped Saturable Absorbing (HDSA) Layer
• 100mW High-Power Angled-Stripe Superluminescent Diodes with a Real Refractive Index Guided Self-Aligned Structure
• Device Modelling of Polymer Light Emitting Diodes
• Resonant-Cavity Photodetectors (Invited Paper)
• A High Performance InAlAs/InGaAs/InP HEMT/MSM-based OEIC Photoreceivers
• A Selective Epitaxial SiGe/Si Planar Photodetector for Si-Based OEICs
• Passive Optical Alignment of Stacked Multi-Fiber Tapes to a Two-Dimensional Surface-Emitting Laser Array

Session 23: Detectors, Sensors and Displays - Micromechanical Devices and Technologies

• A Low-Voltage Bulk-Silicon Tunneling-Based Microaccelerometer
• Lateral Backward Diodes as Strain Sensors
• A Monolithic Thermal Inkjet Printhead Utilizing Electrochemical Etching and Two-Step Electroplating Techniques
• New Convergence Scheme for Self-Consistent Electromechanical Analysis of iMEMS
• Embedded Micromechanical Devices for the Monolithic Integration of MEMS with CMOS
• A Merged MEMS-CMOS Process Using Silicon Wafer Bonding

• Technology of the Future or Nano-Niche?
  Panel Moderator: Paul Peercy, SEMI/SEMATECH, Austin, TX

• FLASH or DRAM: Memory Choice for the Future?
  Panel Moderator: Jim Prendergast, Motorola Semiconductor, Phoenix, AZ

• Body Charge Related Transient Effects in Floating Body SOI NMOSFETs
• Suppression of the Parasitic Biopolar Effect in Ultra-Thin-Film MOSFETs/SIMOX by Ar Ion Implantation into Source/Drain Regions
• SOI MOSFET Design for All-Dimensional Scaling with Short Channel, Narrow Width and Ultrathin Films
• Substantial Advantages of Fully-Depleted CMOS/SIMOX Devices Over Bulk-CMOS Devices as Low-Power High-Performance VLSI Components
• Novel Device Lifetime Behavior and Hot-Carrier Degradation Mechanisms Under VGS = VTH Stress for Thin-Film SOI nMOSFETs
• A Front Gate Charge Pumping Technique for Measuring Both Interfaces in Fully Depleted SOI/MOSFETs
• Dynamic Aging of CMOS SOI Transistors in Circuit Operation

Session 27: Device Interconnect Technology - Advanced Memory Technology

• A 0.54 m2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256Mbit Flash Memories
• A Scalable Low Power Vertical Memory
• 0.228- m2 Trench Cell Technologies with Bottle-Shaped Capacitor for 1G-bit DRAMs
• A Self-Aligned Contact Technology Using Anisotropical Selective Epitaxial Silicon for Giga-Bit DRAMs
• Novel, High-Performance Polysilicon Heterostructure TFTs Using P-I-N Source/Drains
• Bipolar Installed CMOS Technology Without Any Process Step Increase for High Speed Cache SRAM

Session 28: Device Interconnect Technology - Isolation, Gate Dielectrics and Process Integration

• Trench Isolation for 0.45 m Active Pitch and Below
• A New Leakage Component Caused by the Interaction of Residual Stress and the Relative Position of Poly-Si Gate at Isolation Edge
• Characterization and Optimization of NO-Nitrided Gate Oxide by RTP
• A 0.25 m CMOS Technology with 45 NO-Nitrided Oxide
• Low Contact Resistance Metallization for Gigabit Scale DRAMs Using Fully-Dry Cleaning by Ar/H2 ECR Plasma
• Self-Aligned Metal/IDP Si Bipolar Technology Featuring 14 ps/70 GHz

Session 29: Integrated Circuits - High Frequency Si Technologies

• A High Performance MOSFET Design with Highly Controllable Gate Length and Low RC Delay Multilevel Interconnects Technology for High Speed Logic Devices
• Active Substrate Membrane Probe Card
• Extended Study of Crosstalk in SOI-SIMOX Substrates
• Monolithic Planar RF Inductor and Waveguide Structures on Silicon with Performance Comparable to Those in GaAs MMIC
• An Assessment of the State-of-the-Art 0.5 m Bulk CMOS Technology for RF Applications
• Monolithic 26 GHz and 40 GHz VCOs with SiGe Heterojunction Biopolar Transistor
• Discussion Session: Technologies and Tradeoffs for High Performance Passive Elements in Si

Session 30: Solid State Devices - Advanced Bipolar Devices

• SiGe HBT Technology: Device and Application Issues (Invited Paper)
• Very-High fT and fMAX Silicon Bipolar Transistors Using Ultra-High-Performance Super Self-Aligned Process Technology for Low-Energy and Ultra-High-Speed LSI's
• SiGe Base Biopolar Technology with 74 GHzfmax and 11 ps Gate Delay
• Enhanced SiGe Heterojunction Bipolar Transistor Process with 160 GHz-fmax
• Selective-Epitaxial Base Technology with 14ps ECL-GAte Delay, for Low Power Wide-Band Communiction Systems
• Integratable and Low Base Resistance Si/Si1-xGex Heterojunction Bipolar Transistors Using Selective and Non-Selective Rapid Thermal Epitaxy
• Neutral Base Recombination in Advanced SiGe HBTs and Its Impact on the Temperature Characteristics of Precision Analog Circuits

Session 31: Modeling and Simulation - Compound Semiconductor Device Simulation

• Design of Si/SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors
• Monte Carlo Simulation of Electron Transport in Strained SiSi1-xGex n-MOSFETs
• Numerical Simulation of the Temperature Dependence of Band-Edge Photoluminescence and Electroluminescence in Strained-Si1-xGex/Si Heterostructures
• Modeling the Effects of Traps on the IV-Characteristics of GaAs MESFETs
• A Novel Implementation of Noise Analysis in General-Purpose PDE-Based Semiconductor Device Simulators
• Rigorous Two-Dimensional Physical Modeling of Noise Performance of Sub-0.25m Gate-Length FETs

Session 32: Quantum Electronics and Compound Semiconductor Devices - Heterojunction Bipolar Transistors

• High Power AlGaAs/GaAs HBT and Their Applications to Mobile Communication Systems (Invited Paper)
• InGaP/GaAs Power HBTs with Low Bias Voltage
• High-Efficiency X-Band GaInP/GaAs HBT MMIC Power Amplifier for Stable Long Pulse and CW Operation
• Chirped Superlattice Hot Electron Double Heterojunction Bipolar Transistor with High Power Performance at X-Band
• Hybrid Digital/Microwave HBTs for >30 Gb/s Optical Communications Circuits
• 253-GHz fMAX AlGaAs/GaAS HBT with Ni/Ti/Pt/Ti/Pt-Contact and L-Shaped Base Electrode
• Model for Degradation of GaAs/AlGaAs HBTs Under Temperature and Current Stress
• Reliability Investigation of InGaP/GaAs HBTs

Session 33: Detectors, Sensors and Displays - Display and Thin Film Transistor Technologies

• Electroluminescent Devices Using Polymer Blend Thin Films
• Hydrogen Passivation Effects of Performance of Visible Thin-Film Light-Emitting Diodes (TFLEDS)
• Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method
• A PN Gate Polysilicon Thin Film Transistors
• A 2.4-in Driver-Integrated Full Color Quarter VGA (320x3x240) poly-Si TFT LCD by a Novel Low Temperature Process Using Combination ELA and RTA Technology
• VGA Driving with Low Temperature Processed Poly Si TFTs

• Performance and Reliability Concerns of Ultra-thin SOI and Ultra-thin Gate Oxide MOSFETS (Invited Paper)
• Direct Tunneling N2O Gate Oxynitrides for Low-Voltage Operation of Dual Gate CMOSFETs
• Highly-Reliable Gate Oxide Formation for Giga-Scale LSIs by Using Closed Wet Cleaning System and Wet Oxidation with Ultra-Dry Unloading
• Impact of Surface Proximity Gettering and Nitrided Oxide Side-Wall Spacer by Nitrogen Implantation on Sub-Quarter Micron CMOS LDD FETs
• A Consistent Model for the Thickness Dependence of Intrinsic Breakdown in Ultra-thin Oxides
• High Endurance Ultra-Thin Tunnel Oxide for Dynamic Memory Application A New Degradation Mode of Scaled p+ Polysilicon Gate pMOSFETs Induced by Bias Temperature (BT) Instability

Session 35: Device Interconnect Technology - Technologies for Low-Voltage/Low Power Applications in the Sub Quarter Micron Regime

• Back Gated CMOS on SOIAS for Dynamic Threshold Voltage Control
• Threshold Voltage Adjustment in SOI MOSFETs by Employing Tantalum for Gate Material
• Controlling the Device Field Edge to Achieve a Low Voltage/Low Power TFSOI Technology
• Giga-bit DRAM Cell with Low Capacitance and Low Resistance Bit-lines on Buried MOSFETs and Capacitors by Using Bonded SOI Technology
• W-Polycide Dual-Gate Structure for Sub-1/4 Micron Low-Voltage CMOS Technology
• Re-Examination of Indium Implantation for a Low Power 0.1 um Technology

Session 36: Integrated Circuits - Advanced DRAM and SRAM Devices

• Giga-Bit Scale DRAM Cell with New Simple Ru/(Ba,Sr)TiO3/Ru Stacked Capacitors Using X-ray Lithography
• A Process Technology for a 1 Giga-Bit DRAM
• Isolation-Merged Bit Line Cell (IMBC) for 1Gb DRAM and Beyond
• Well Concentration: A Novel Scaling Limitation Factor from DRAM Retention Time and Its Modeling
• Using n-Channel TFTs without LDD Structures for High Stabilities of 1.2-V High-Density SRAMS
• A 0.35 m ECL_CMOS Process Technology on SOI for 40ps Logic and 1ns Mega-bits SRAMs
• High Performance 0.25 m SRAM Technology with Tungsten Interpoly Plug

Session 37: Modeling and Simulation - Compact MOS Modeling

• A Computationally Efficient Model for Inversion Layer Quantization Effects in Deep Submicron N-Channel MOSFETs
• A Physical Compact MOSFET Model, Including Quantum Mechanical Effects, for Statistical Circuit Design Applications
• Circuit Sensitivity Analysis in Terms of Process Parameters
• Efficient Non-Quasi-Static MOSFET's Model for Circuit Simulation
• A Physically Based Device Model for Fully Depleted and Nearly Fully Depleted SOI MOSFET
• A Physical-Based Analytical Turn-On Model of PolySilicon Thin Film Transistors for Circuit Simulation

Session 38: Solid State Devices - Power ICs

• Power IC's Move Ink Jet Printers to New Performance Levels (Invited Paper)
• A Novel LDMOS Structure with A Step Gate Oxide
• High Voltage BiCMOS Technology on Bonded 2 m SOI Integrating Vertical pnp npn, 60V-LDMOS and MPU, Capable of 200 C Operation
• An Effective Cross-Talk Isolation Structure for Power IC Applications
• Integration of a Novel High-Voltage Giga-hertz DMOS Transistor Into a Standard CMOS Process
• Fully depleted 30-V-Class Thin-Film SOI Power MOSFET
• Optimization of High Q Integrated Inductors in Multi Level Metal CMOS