Solid State Circuits Technology Workshop on CMOS Imaging Technology
Wednesday, 7 February 1996
San Francisco Marriott Hotel, San Francisco, CA
Workshop Proceedings
The recent advances in CMOS-technology have opened the possibility of imagers offering significant
improvements in the functionality, power and cost of digital video and still cameras. The advent
of sub-micron CMOS-technology allows pixels which contain several FETs and are circuits in their
own right to be comparable in size to those existing on commercial CCD imagers . Fabrication on
standard CMOS process lines permits these imagers to be fully integrated with digital circuitry to
create single-chip camera systems.
The intent of this workshop was to bring together researchers, developers, and potential users of
CMOS imaging technology to share their ongoing work and to acquaint circuit designers with
the possibilities provided by the merging of CMOS and imaging. The program lasted day with a
series of 30 minute talks and 10 minutes discussion and question periods.
Program:
- Introductory Remarks,
R. Daniel McGrath, Polaroid Corp.
- Operation & analysis of CMOS active pixel sensors,
Bedabrata Pain, JPL
- Building & comparing passive & active pixels,
Peter Denyer, VLSI Vision Limited, UK
- Large area array with non-linear active current-mode
pixels, Vince Clark, Polaroid
- Fixed-pattern noise reduction techniques in CMOS
imaging arrays, Steve Decker, MIT
- A 1024x1024 CMOS active pixel image sensor,
Alex Dickinson, AT&T Bell Labs
- Color signal processing for CMOS active pixel sensor,
David Gibbons, AT&T Bell Labs
- Analog CMOS implementation of low-level vision chips for low-power & real-time
applications, Xavier Arreguit, CSEM, Switzerland
- Technology & device scaling considerations for
CMOS imagers, Philip Wong, IBM
Organizers:
Alex Dickinson (AT&T Bell Labs) 908-949-1083 alex @ big.att.com
Dan McGrath (Polaroid Corp) 617-386-8792 mcgratd @ polaroid.com