8:40 - 9:40 Keynote: The Memory Gap, Maurice Wilkes, AT&T Research Laboratories, Cambridge

• DDR2 and Low latency Variants, B. Davis, T. Mudge, University of Michigan, B. Jacob, V. Cuppu, University of Maryland

• A Case for Asynchronous Active Memories, R. Manohar, M. Heinrich, Cornell University

• Investigation into the Use of Processors in Memory for Volume Rendering, A. K. Snip, D. G. Elliott, M. Margala, N. G. Durdle, University of Alberta

• A Packaging Assault on the Memory Wall, B. Montoye, P. Hofstee, IBM Austin Research Laboratory

• Hardware Support for Dynamic Memory Management, J. M. Chang, W. Srisa-an, C. D. Lo, Illinois Institute of Technology, E.F. Gehringer, North Carolina State University

• Cache Coherence in Intelligent Memory Systems, D. Keen, M. Oskin, J. Hensley, F. T. Chong, UC Davis

• Dynamic Memory Hierarchy Performance Optimization, R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas, University of Rochester

• Cache-Memory Interfaces in Compressed Memory Systems, C. D. Benveniste, P. A. Franaszek, J. T. Robinson, IBM T. J. Watson Research Center

• Operating System Support for Fast Hardware Compression of Main Memory Contents, B. Abali, H. Franke, IBM T. J. Watson Research Center

3:50 - 4:30 Invited Talk, A Memory Technology Outlook and Retrospective, Larry Sadwick, University of Utah

• Pointer-Based Prefetching within the Impulse Adaptable Memory Controller: Initial Results, L. Zhang, S. A. McKee, W. C. Hsieh, J. B. Carter, University of Utah

• Array Contraction for Memory Reduction, Y. Song, R. Xu, C. Wang, Z. Li, Purdue University

• Compiler Transformations for Exploiting Bandwidth in PIM-Based Systems, J. Chame, J. Shin, M. Hall, USC-ISI

• Multi-Chain Prefetching : Exploiting Memory Parallelism in Pointer-Chasing Codes, N. Kohout, S. Choi, D. Yeung, University of Maryland