GPGPU5
Fifth Workshop on General Purpose Processing on Graphics Processing Units

Held with ASPLOS XVII
March 3, 2012
London, UK

Overview:

Overview: The goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming environments and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year's work is particularly interested on new heterogeneous GPU platforms. The final program can be found HERE . The workshop proceedings will be published in the ACM Online Conference Proceedings Series. Selected paper will be selected for a special issue of the Journal of Parallel Processing.

Registration and Venue Information:

Please refer to the ASPLOS 2012 website for registration and local information. The Workshop will be held in the Royal Society in the Library Events Room.

Keynote: An Introduction to GCN - Norman Rubin, AMD Fellow


Abstract: AMD recently introduced a new GPU architecture: GCN (graphics core next). This architecture is rolling out in discrete graphics cards now and in APU processors in future years. The GCN core was designed from the ground up for modern graphics and compute workloads. For AMD, GCN is the biggest architecture overhaul since R600 in 2007. In GCN we moved to a new vector shader architecture, with high level language support and unified caches. Heterogeneous computing is the key to power efficient processing for modern workloads beyond graphics. The GCN core in both discrete GPUs and APUs thrives on these workloads.

This talk will look at GCN and will explain what changed and why. The Radeon HD7970 is the first product to feature GCN. This is the first graphics card based on a 28nm silicon node, the first to support dx 11.1, and the fastest single chip graphics card in the world. Read more about it here.

About the speaker: Norm Rubin has over thirty years of experience delivering commercial compilers for processors ranging from embedded (ARM), desktop (HP, ALPHA) and supercomputer (KSR), and is a recognized expert in the field.

He was the architect and lead implementer for the widely used graphics compiler for AMD/ATI. That compiler is currently shipping on millions of machines including cell phones, consoles, and PCs. For the last several years, Norm has been part of the AMD architecture team working on the design of the next generation AMD system architecture where he has been working on byte code language design.

Norm holds a PhD from the Courant Institute of NYU. Besides his work in compilers, he is well known for his work in compiler related parts of the tool chain, binary translators and dynamic optimizers.

Organizing Committee

David Kaeli, Northeastern Univ.

John Cavazos, University of Delaware

Program Committee


Tarek Abdelrahman, Toronto
Emmanuel Agu, WPI
Martin Burtscher, Texas State
John Cavazos, U Delaware
Jason Choy, JP Morgan Chase
Albert Cohen, INRIA
Michael Gschwind, IBM
Lee Howes, AMD
Byunghyun Jang, AMD
Richard Johnson, NVIDIA
David Jones, Imperial College
David Kaeli, Northeastern
Volodymyr Kindratenko, UIUC
Jaejin Lee, Seoul National University
Anton Lokhmotov, ARM
Avi Mendelson, Microsoft Israel
Vincent Natoli, Stoneridge
Nacho Navarro, UPC Barcelona
Nicholas Pinto, Harvard/MIT
Hridesh Rajan, Iowa State
Norman Rubin, AMD
Markus Schordan, UAS Technikum Wien
Xipeng Shen, William & Mary
Sudharkar Yalamanchili, Georgia Tech

Updated on March 1, 2012